[llvm] 7511303 - [DAG] canCreateUndefOrPoison - add freeze(fsh(x,y,z)) -> fsh(freeze(x),freeze(y),freeze(z)) support

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-10-22T18:39:52+01:00
New Revision: 7511303c4fb05027b27180e7255462b7626aa1cf

URL: https://github.com/llvm/llvm-project/commit/7511303c4fb05027b27180e7255462b7626aa1cf
DIFF: https://github.com/llvm/llvm-project/commit/7511303c4fb05027b27180e7255462b7626aa1cf.diff

LOG: [DAG] canCreateUndefOrPoison - add freeze(fsh(x,y,z)) -> fsh(freeze(x),freeze(y),freeze(z)) support

The funnel-shift amount is always modulo, so won't introduce poison/undef

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/test/CodeGen/X86/freeze-binary.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 95c309b02991..da02a2816f8a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4628,6 +4628,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
   case ISD::XOR:
   case ISD::ROTL:
   case ISD::ROTR:
+  case ISD::FSHL:
+  case ISD::FSHR:
   case ISD::BSWAP:
   case ISD::CTPOP:
   case ISD::BITREVERSE:

diff  --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll
index 3f4dfb26f9b5..1807fc72eb35 100644
--- a/llvm/test/CodeGen/X86/freeze-binary.ll
+++ b/llvm/test/CodeGen/X86/freeze-binary.ll
@@ -712,16 +712,15 @@ define i32 @freeze_fshl(i32 %a0, i32 %a1, i32 %a2) nounwind {
 ; X86-LABEL: freeze_fshl:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    shrdl $27, %ecx, %eax
-; X86-NEXT:    shldl $27, %edx, %eax
+; X86-NEXT:    shrl $27, %eax
+; X86-NEXT:    shldl $27, %ecx, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: freeze_fshl:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    shldl $5, %esi, %eax
+; X64-NEXT:    movl %esi, %eax
+; X64-NEXT:    shrl $27, %eax
 ; X64-NEXT:    shldl $27, %edx, %eax
 ; X64-NEXT:    retq
   %f1 = freeze i32 %a1
@@ -736,16 +735,15 @@ define i32 @freeze_fshr(i32 %a0, i32 %a1, i32 %a2) nounwind {
 ; X86-LABEL: freeze_fshr:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    shrdl $1, %ecx, %eax
-; X86-NEXT:    shldl $1, %edx, %eax
+; X86-NEXT:    shrl %eax
+; X86-NEXT:    shldl $1, %ecx, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: freeze_fshr:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    shldl $31, %esi, %eax
+; X64-NEXT:    movl %esi, %eax
+; X64-NEXT:    shrl %eax
 ; X64-NEXT:    shldl $1, %edx, %eax
 ; X64-NEXT:    retq
   %f1 = freeze i32 %a1