[PATCH] D136531: [TableGen] Fix sub-operand counting bug in PseudoLoweringEmitter

[Sergei Barannikov via Phabricator via llvm-commits]

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When generating expansion for instruction with complex operands, the
`BaseIdx` variable was not properly updated. This resulted in
spurious error messages about mismatched operands.
The fix is a copy-and-paste from the last 'else if' statement.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136531

Files:
  llvm/test/TableGen/pseudo-inst-expansion.td
  llvm/utils/TableGen/PseudoLoweringEmitter.cpp


Index: llvm/utils/TableGen/PseudoLoweringEmitter.cpp
===================================================================
--- llvm/utils/TableGen/PseudoLoweringEmitter.cpp
+++ llvm/utils/TableGen/PseudoLoweringEmitter.cpp
@@ -104,6 +104,8 @@
       for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
         OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
       OpsAdded += Insn.Operands[i].MINumOperands;
+      // Since we added more than one, we also need to adjust the base.
+      BaseIdx += Insn.Operands[i].MINumOperands - 1;
     } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) {
       OperandMap[BaseIdx + i].Kind = OpData::Imm;
       OperandMap[BaseIdx + i].Data.Imm = II->getValue();
Index: llvm/test/TableGen/pseudo-inst-expansion.td
===================================================================
--- llvm/test/TableGen/pseudo-inst-expansion.td
+++ llvm/test/TableGen/pseudo-inst-expansion.td
@@ -35,3 +35,23 @@
              PseudoInstExpansion<(INSTR GPR:$rd, SR.Encoding)>;
 
 // CHECK: .addOperand(MCOperand::createImm(3855));
+
+def ComplexOp : Operand<i32> { let MIOperandInfo = (ops GPR, i32imm); }
+
+def INSTR2 : Instruction {
+  let OutOperandList = (outs);
+  let InOperandList = (ins ComplexOp:$cop, GPR:$r);
+}
+
+def PSEUDO2 : Pseudo<(outs), (ins ComplexOp:$cop), []>,
+              PseudoInstExpansion<(INSTR2 ComplexOp:$cop, REG)>;
+
+// CHECK:      TmpInst.setOpcode(::INSTR2);
+// CHECK-NEXT: // Operand: cop
+// CHECK-NEXT: lowerOperand(MI->getOperand(0), MCOp);
+// CHECK-NEXT: TmpInst.addOperand(MCOp);
+// CHECK-NEXT: lowerOperand(MI->getOperand(1), MCOp);
+// CHECK-NEXT: TmpInst.addOperand(MCOp);
+// CHECK-NEXT: // Operand: r
+// CHECK-NEXT: TmpInst.addOperand(MCOperand::createReg(::REG));
+// CHECK-NEXT: EmitToStreamer(OutStreamer, TmpInst);


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