[PATCH] D136529: [DAG] canCreateUndefOrPoison - add support for SRA/SRL shift opcode (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

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Right shifts won't create undef/poison if they are exact with inrange shift amounts.

Matches handling in Operator::hasPoisonGeneratingFlags()

WIP: There are still a few regression cases to handle (either other missing opcodes or we are freezing ops that we can't push the freeze through multiple operands), but I'm cleaning out old branches and wanted to get this up for future reference.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136529

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AMDGPU/sdiv64.ll
  llvm/test/CodeGen/AMDGPU/srem64.ll
  llvm/test/CodeGen/AMDGPU/udiv64.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/X86/freeze-binary.ll
  llvm/test/CodeGen/X86/midpoint-int-vec-512.ll

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