[PATCH] D135683: [AArch64]SME2 single-multi and multi-multi FP dot product instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2302-2303
+
+multiclass sme2_fp_dot_array_vg2_multi<string mnemonic, bit op> {
+  def NAME : sme2_fp_dot_array_vg24_multi<op, ZZ_h_mul_r, mnemonic, "vgx2">{
+    bits<4> Zm;
----------------
This to me looks almost identical too `sme2_mla_add_sub_array_vg2_multi` which makes sense given they share the same encoding parent `SME2 Multi-vector - Multiple Array Vectors (Two registers)`. I think you're focusing too much on trying to share instruction definitions between vg2 and vg4 whereas looking at the encoding groups they typically sit in different tables.  This means your having to create far more instruction/base classes than you need to.

I'm not saying everything in `SME2 Multi-vector - Multiple Array Vectors (Two registers)` can be represented using a single instruction/base class but many take the form `ZA.S[<Wv>, <imm>{, VGx2}], { <Zn1>.?-<Zn2>.? }, { <Zm1>.?-<Zm2>.? }` and so I'd expect much more reuse than is currently the case.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D135683/new/

https://reviews.llvm.org/D135683