[PATCH] D135601: [AArch64]SME2 Multiple vectors Int/FP clamp instructions for two/four registers

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1988
+  bits<4> Zd;
+  let Inst{11}  = 0b0;
+  let Inst{4-1} = Zd;
----------------
CarolineConcatto wrote:
> paulwalker-arm wrote:
> > The base class shows value here but what about making `op1` a two bit opcode?
> I did not do this because this class is also used by:
> sme2_int_clamp_vector_vg2_multi
> that needs to set the value o//** u**//  in AArch64SMEInstrInfo.td.
> 
> I can change class sme2_clamp_vector_vg2_multi, and then change  the multiclass sme2_int_clamp_vector_vg2_multi to be
> multiclass sme2_int_clamp_vector_vg2_multi<string mnemonic, bits<2> u>
> instead of only 
> multiclass sme2_int_clamp_vector_vg2_multi<string mnemonic, bit u>
> If you see value in doing that.
I'm not sure where `u` comes into it.  I am referring to the fact that `sme2_clamp_vector_vg24_multi` does not set `Inst{11}`, however both `sme2_clamp_vector_vg2_multi` and `sme2_clamp_vector_vg4_multi` set `Inst{11}` and thus I'm proposing that rather than them setting it explicitly you could just make `op1` represent `Inst{11--10}`?


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135601/new/

https://reviews.llvm.org/D135601