[PATCH] D136433: [GlobalISel][AArch64] Fix miscompile caused by wrong G_ZEXT selection in GISel

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 updated this revision to Diff 469849.
bcl5980 retitled this revision from "[AArch64] Fix miscompile caused by subreg_to_reg" to "[GlobalISel][AArch64] Fix miscompile caused by wrong G_ZEXT selection in GISel".
bcl5980 edited the summary of this revision.
bcl5980 added a comment.
Herald added a subscriber: rovka.

Update by @efriedma 's comment.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136433/new/

https://reviews.llvm.org/D136433

Files:
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/pr58431.ll


Index: llvm/test/CodeGen/AArch64/pr58431.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/pr58431.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=0 | FileCheck %s
+
+define i32 @f(i64 %0) {
+; CHECK-LABEL: f:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #10
+; CHECK-NEXT:    mov w9, w0
+; CHECK-NEXT:    udiv x10, x9, x8
+; CHECK-NEXT:    msub x0, x10, x8, x9
+; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT:    ret
+  %2 = trunc i64 %0 to i32
+  %3 = freeze i32 %2
+  %4 = zext i32 %3 to i64
+  %5 = urem i64 %4, 10
+  %6 = trunc i64 %5 to i32
+  ret i32 %6
+}
Index: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
===================================================================
--- llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -6839,6 +6839,7 @@
   case TargetOpcode::G_BITCAST:
   case TargetOpcode::G_TRUNC:
   case TargetOpcode::G_PHI:
+  case TargetOpcode::G_FREEZE:
     return false;
   }
 }


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