[PATCH] D129735: [WIP][RISCV] Add new pass to transform undef to pesudo for vector values.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I remember now. It only miscompiles with `-riscv-enable-subreg-liveness`

That produces

  foo:                                    # @foo
          .cfi_startproc
  # %bb.0:                                # %loopIR.preheader.i.i
          vsetvli a0, zero, e16, mf4, ta, ma
          vid.v   v8
          vadd.vi v10, v8, 1
          vadd.vi v12, v8, 3
  .LBB0_1:                                # %loopIR3.i.i
                                          # =>This Inner Loop Header: Depth=1
          vl1r.v  v9, (zero)
          vsetivli        zero, 4, e8, m1, ta, ma
          vrgatherei16.vv v11, v9, v8
          vrgatherei16.vv v13, v9, v10
          vsetvli a0, zero, e8, m1, ta, ma
          vand.vv v11, v11, v13
          vsetivli        zero, 4, e8, m1, ta, ma
          vrgatherei16.vv v13, v9, v12 <- this instruction violates the early clobber constraint
          vsetvli a0, zero, e8, m1, ta, ma
          vand.vv v9, v11, v13
          vs1r.v  v9, (zero)
          j       .LBB0_1
  .Lfunc_end0:
          .size   foo, .Lfunc_end0-foo
          .cfi_endproc
                                          # -- End function                        
          .section        ".note.GNU-stack","", at progbits


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