[PATCH] D136478: [LegalizeDAG][X86] Expand vector S/USHLSAT instead of unrolling.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Not entirely sure if this is generaly good given X86's poor variable
shuffle support in earlier SSE versions.

These are very undertested intrinsics. I can improve that, but wanted
to get feedback if this generally made sense or if we needed a way
to limit to cases that have good variable shift support.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136478

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/X86/sshl_sat_vec.ll
  llvm/test/CodeGen/X86/ushl_sat_vec.ll

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