[PATCH] D135601: [AArch64]SME2 Multiple vectors Int/FP clamp instructions for two/four registers

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1988
+  bits<4> Zd;
+  let Inst{11}  = 0b0;
+  let Inst{4-1} = Zd;
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The base class shows value here but what about making `op1` a two bit opcode?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135601/new/

https://reviews.llvm.org/D135601