[llvm] d78c3b3 - [AArch64][SVE2] Add the SVE2.1 fclamp instructions
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 21 07:33:22 PDT 2022
Author: David Sherwood
Date: 2022-10-21T14:33:16Z
New Revision: d78c3b320287dde5808f62167186c383e6871a1b
URL: https://github.com/llvm/llvm-project/commit/d78c3b320287dde5808f62167186c383e6871a1b
DIFF: https://github.com/llvm/llvm-project/commit/d78c3b320287dde5808f62167186c383e6871a1b.diff
LOG: [AArch64][SVE2] Add the SVE2.1 fclamp instructions
This patch adds the assembly/disassembly for the following instructions:
FCLAMP : Floating-point clamp to minimum/maximum number
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D136358
Added:
llvm/test/MC/AArch64/SVE2p1/fclamp-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/fclamp.s
Modified:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index f9b4e5dcb0f0..d79fcc525233 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3568,3 +3568,11 @@ defm UCLAMP_ZZZ : sve2_clamp<"uclamp", 0b1, int_aarch64_sve_uclamp>;
defm PSEL_PPPRI : sve2_int_perm_sel_p<"psel", int_aarch64_sve_psel>;
} // End HasSVE2p1_or_HasSME
+
+//===----------------------------------------------------------------------===//
+// SME2 or SVE2.1 instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasSVE2p1_or_HasSME2] in {
+defm FCLAMP_ZZZ : sve2p1_fclamp<"fclamp">;
+} // End HasSVE2p1_or_HasSME2
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index fe51a1d6d7af..17c90abf8cf7 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -8601,3 +8601,32 @@ multiclass sve_int_bin_pred_all_active_bhsd<SDPatternOperator op> {
def : SVE_2_Op_Pred_All_Active_Pt<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Pseudo>(NAME # _UNDEF_D)>;
}
+//===----------------------------------------------------------------------===//
+// SME2 or SVE2.1 Instructions
+//===----------------------------------------------------------------------===//
+
+class sve2p1_fclamp<string asm, bits<2> sz, ZPRRegOp zpr_ty>
+ : I<(outs zpr_ty:$Zd), (ins zpr_ty:$_Zd, zpr_ty:$Zn, zpr_ty:$Zm),
+ asm, "\t$Zd, $Zn, $Zm", "", []>,
+ Sched<[]> {
+ bits<5> Zm;
+ bits<5> Zn;
+ bits<5> Zd;
+ let Inst{31-24} = 0b01100100;
+ let Inst{23-22} = sz;
+ let Inst{21} = 0b1;
+ let Inst{20-16} = Zm;
+ let Inst{15-10} = 0b001001;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zd;
+
+ let Constraints = "$Zd = $_Zd";
+ let DestructiveInstType = DestructiveOther;
+ let ElementSize = zpr_ty.ElementSize;
+}
+
+multiclass sve2p1_fclamp<string asm> {
+ def _H : sve2p1_fclamp<asm, 0b01, ZPR16>;
+ def _S : sve2p1_fclamp<asm, 0b10, ZPR32>;
+ def _D : sve2p1_fclamp<asm, 0b11, ZPR64>;
+}
diff --git a/llvm/test/MC/AArch64/SVE2p1/fclamp-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/fclamp-diagnostics.s
new file mode 100644
index 000000000000..b0a69969f958
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/fclamp-diagnostics.s
@@ -0,0 +1,14 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+fclamp z23.h, z23.s, z13.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fclamp z23.h, z23.s, z13.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fclamp z23.s, z23.d, z13.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fclamp z23.s, z23.d, z13.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/fclamp.s b/llvm/test/MC/AArch64/SVE2p1/fclamp.s
new file mode 100644
index 000000000000..bd52cba1d31f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/fclamp.s
@@ -0,0 +1,110 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+movprfx z23, z31
+fclamp z23.d, z13.d, z8.d // 01100100-11101000-00100101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: fclamp z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x25,0xe8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e825b7 <unknown>
+
+fclamp z0.d, z0.d, z0.d // 01100100-11100000-00100100-00000000
+// CHECK-INST: fclamp z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x24,0xe0,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e02400 <unknown>
+
+fclamp z21.d, z10.d, z21.d // 01100100-11110101-00100101-01010101
+// CHECK-INST: fclamp z21.d, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0x25,0xf5,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64f52555 <unknown>
+
+fclamp z23.d, z13.d, z8.d // 01100100-11101000-00100101-10110111
+// CHECK-INST: fclamp z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x25,0xe8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e825b7 <unknown>
+
+fclamp z31.d, z31.d, z31.d // 01100100-11111111-00100111-11111111
+// CHECK-INST: fclamp z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x27,0xff,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64ff27ff <unknown>
+
+movprfx z23, z31
+fclamp z23.h, z13.h, z8.h // 01100100-01101000-00100101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: fclamp z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x25,0x68,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 646825b7 <unknown>
+
+fclamp z0.h, z0.h, z0.h // 01100100-01100000-00100100-00000000
+// CHECK-INST: fclamp z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x24,0x60,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64602400 <unknown>
+
+fclamp z21.h, z10.h, z21.h // 01100100-01110101-00100101-01010101
+// CHECK-INST: fclamp z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x25,0x75,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64752555 <unknown>
+
+fclamp z23.h, z13.h, z8.h // 01100100-01101000-00100101-10110111
+// CHECK-INST: fclamp z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x25,0x68,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 646825b7 <unknown>
+
+fclamp z31.h, z31.h, z31.h // 01100100-01111111-00100111-11111111
+// CHECK-INST: fclamp z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x27,0x7f,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 647f27ff <unknown>
+
+movprfx z23, z31
+fclamp z23.s, z13.s, z8.s // 01100100-10101000-00100101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: fclamp z23.s, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0x25,0xa8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64a825b7 <unknown>
+
+fclamp z0.s, z0.s, z0.s // 01100100-10100000-00100100-00000000
+// CHECK-INST: fclamp z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x24,0xa0,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64a02400 <unknown>
+
+fclamp z21.s, z10.s, z21.s // 01100100-10110101-00100101-01010101
+// CHECK-INST: fclamp z21.s, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0x25,0xb5,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64b52555 <unknown>
+
+fclamp z23.s, z13.s, z8.s // 01100100-10101000-00100101-10110111
+// CHECK-INST: fclamp z23.s, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0x25,0xa8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64a825b7 <unknown>
+
+fclamp z31.s, z31.s, z31.s // 01100100-10111111-00100111-11111111
+// CHECK-INST: fclamp z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x27,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64bf27ff <unknown>
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