[PATCH] D136439: [AArch64][SVE2] Add the SVE2.1 bfmlslb and bfmlslt instructions

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td:2051
 // Multiply accumulate long
 def : InstRW<[N2Write_4cyc_1V], (instregex "^BFMLAL[BT]_ZZ[ZI]$")>;
 
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I suspect the reason the scheduler model failed to compile is this regex no longer matches and the model is marked as complete? The regex should now be `^BFMLAL[BT]_ZZZI?$`, although I don't really get how what you did fixed this.


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  https://reviews.llvm.org/D136439/new/

https://reviews.llvm.org/D136439