[PATCH] D136339: [MachineCombiner][RISCV] Relax optimization level requirement

[Anton Sidorenko via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG14a5b9cdaefe: [MachineCombiner][RISCV] Relax optimization level requirement (authored by asi-sc).

Changed prior to commit:
  https://reviews.llvm.org/D136339?vs=469178&id=469535#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136339/new/

https://reviews.llvm.org/D136339

Files:
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
  llvm/test/CodeGen/RISCV/machine-combiner.ll


Index: llvm/test/CodeGen/RISCV/machine-combiner.ll
===================================================================
--- llvm/test/CodeGen/RISCV/machine-combiner.ll
+++ llvm/test/CodeGen/RISCV/machine-combiner.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \
-; RUN: -O3 -riscv-enable-machine-combiner=true < %s | \
+; RUN: -O1 -riscv-enable-machine-combiner=true < %s | \
 ; RUN: FileCheck %s
 
 define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) {
Index: llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
===================================================================
--- llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
+++ llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \
-; RUN: -O3 -riscv-enable-machine-combiner=true        \
+; RUN: -O1 -riscv-enable-machine-combiner=true        \
 ; RUN: -stop-after machine-combiner < %s | FileCheck %s
 
 define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) {
Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -268,7 +268,7 @@
 
 void RISCVPassConfig::addMachineSSAOptimization() {
   TargetPassConfig::addMachineSSAOptimization();
-  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableMachineCombiner)
+  if (EnableMachineCombiner)
     addPass(&MachineCombinerID);
 
   if (TM->getTargetTriple().getArch() == Triple::riscv64)


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D136339.469535.patch
Type: text/x-patch
Size: 1817 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221021/10b59ef2/attachment.bin>