[llvm] 14a5b9c - [MachineCombiner][RISCV] Relax optimization level requirement

[Anton Sidorenko via llvm-commits]

Author: Anton Sidorenko
Date: 2022-10-21T13:25:28+03:00
New Revision: 14a5b9cdaefee281dbd3814cf0ae04d728a90a30

URL: https://github.com/llvm/llvm-project/commit/14a5b9cdaefee281dbd3814cf0ae04d728a90a30
DIFF: https://github.com/llvm/llvm-project/commit/14a5b9cdaefee281dbd3814cf0ae04d728a90a30.diff

LOG: [MachineCombiner][RISCV] Relax optimization level requirement

Enable Machine Combiner for O1/O2/O3 optimization levels. It makes RISCV
consistent with other targets running Machine Combiner.

Originally it was enabled only for -O3, however I looked through time reports
and usually it takes 0.1%-0.4% of total time, and never takes more than 1.0%.

Differential Revision: https://reviews.llvm.org/D136339

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
    llvm/test/CodeGen/RISCV/machine-combiner.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 02d3c47bb1a43..2f5ea98c7d4d0 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -268,7 +268,7 @@ void RISCVPassConfig::addPreEmitPass2() {
 
 void RISCVPassConfig::addMachineSSAOptimization() {
   TargetPassConfig::addMachineSSAOptimization();
-  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableMachineCombiner)
+  if (EnableMachineCombiner)
     addPass(&MachineCombinerID);
 
   if (TM->getTargetTriple().getArch() == Triple::riscv64)

diff  --git a/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll b/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
index adb05ee50697e..9965fa96e8719 100644
--- a/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
+++ b/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \
-; RUN: -O3 -riscv-enable-machine-combiner=true        \
+; RUN: -O1 -riscv-enable-machine-combiner=true        \
 ; RUN: -stop-after machine-combiner < %s | FileCheck %s
 
 define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) {

diff  --git a/llvm/test/CodeGen/RISCV/machine-combiner.ll b/llvm/test/CodeGen/RISCV/machine-combiner.ll
index 6d9a7e9268069..58e5ed9d77b8d 100644
--- a/llvm/test/CodeGen/RISCV/machine-combiner.ll
+++ b/llvm/test/CodeGen/RISCV/machine-combiner.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \
-; RUN: -O3 -riscv-enable-machine-combiner=true < %s | \
+; RUN: -O1 -riscv-enable-machine-combiner=true < %s | \
 ; RUN: FileCheck %s
 
 define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) {