[PATCH] D136169: [AMDGPU] Avoid SCC clobbering before S_CSELECT_B32

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

Am I correct to assume that frame offset is always DWORD aligned? If so we have couple spare bits:

  S_ADDC_U32 $reg, offset
  S_BITCMP1_B32 $reg, 0
  S_BITSET0_B32 $reg, 0


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  https://reviews.llvm.org/D136169/new/

https://reviews.llvm.org/D136169