[PATCH] D136296: [AArch64] Fix scheduler crash in fusion code.

[Eli Friedman via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGdecb743e80df: [AArch64] Fix scheduler crash in fusion code. (authored by efriedma).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136296/new/

https://reviews.llvm.org/D136296

Files:
  llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
  llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir


Index: llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
@@ -0,0 +1,29 @@
+# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=cortex-x1 -run-pass=machine-scheduler
+# Just ensure this doesn't crash.
+
+---
+name: crash
+tracksRegLiveness: true
+body: |
+  bb.0:
+    successors: %bb.1(0x00000000), %bb.2(0x80000000)
+    liveins: $w0, $x1
+
+    %1:gpr64common = COPY $x1
+    %0:gpr32common = COPY $w0
+    %3:gpr64sp = COPY $xzr
+    INLINEASM &"", 9 /* sideeffect mayload attdialect */, 196622 /* mem:m */, %3
+    %4:gpr32 = ADDSWri %0, 1, 0, implicit-def $nzcv
+    STRWui %4, %1, 0 :: (store (s32))
+    Bcc 3, %bb.2, implicit killed $nzcv
+    B %bb.1
+
+  bb.1:
+    successors:
+
+    ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+    ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+
+  bb.2:
+    RET_ReallyLR
+...
Index: llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
+++ llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
@@ -30,8 +30,9 @@
 
   // If we're in CmpOnly mode, we only fuse arithmetic instructions that
   // discard their result.
-  if (CmpOnly && !(FirstMI->getOperand(0).getReg() == AArch64::XZR ||
-                   FirstMI->getOperand(0).getReg() == AArch64::WZR)) {
+  if (CmpOnly && FirstMI->getOperand(0).isReg() &&
+      !(FirstMI->getOperand(0).getReg() == AArch64::XZR ||
+        FirstMI->getOperand(0).getReg() == AArch64::WZR)) {
     return false;
   }
 


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