[PATCH] D136366: [PowerPC] Add new DMR register classes to Future CPU.

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp created this revision.
stefanp added reviewers: lei, amyk, nemanjai.
Herald added subscribers: shchenz, kbarton, hiraditya, dschuff.
Herald added a project: All.
stefanp requested review of this revision.
Herald added subscribers: jdoerfert, aheejin.
Herald added a project: LLVM.

A new register class as well as a number of related subregisters are being added
to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits
long. These regsiters can also be used in consecutive pairs which leads to a
register that is 2048 bits.

This patch also adds 7 new instructions that use these registers. More
instructions will be added in future patches.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136366

Files:
  llvm/include/llvm/CodeGen/ValueTypes.td
  llvm/include/llvm/IR/Intrinsics.td
  llvm/include/llvm/Support/MachineValueType.h
  llvm/lib/CodeGen/ValueTypes.cpp
  llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
  llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
  llvm/lib/Target/PowerPC/PPCInstrFuture.td
  llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/lib/Target/PowerPC/PPCRegisterInfoDMR.td
  llvm/lib/Target/PowerPC/PPCScheduleP9.td
  llvm/test/CodeGen/PowerPC/future-check-features.ll
  llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
  llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
  llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
  llvm/utils/TableGen/CodeGenTarget.cpp

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