[PATCH] D135567: [AArch64] SME2 Multiple vectors int/float binary accumulator and two/four ZA single-vector

[Caroline via Phabricator via llvm-commits]

CarolineConcatto added inline comments.


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Comment at: llvm/test/MC/AArch64/SME2/add.s:41
+add     za.s[w8, 0, vgx2], {z0.s-z1.s}  // 11000001-10100000-00011100-00010000
+// CHECK-INST: add     za.s[w8, 0, vgx2], { z0.s-z1.s }
+// CHECK-ENCODING: [0x10,0x1c,0xa0,0xc1]
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david-arm wrote:
> Is this output still correct? I was expecting the vector list to be printed out as `{ z0.s, z1.s }`. Perhaps this patch just needs a rebase?
Yes, it was not rebased on the changes for the printVectorList


Repository:
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  https://reviews.llvm.org/D135567/new/

https://reviews.llvm.org/D135567