[llvm] c66426f - [RISCV] Remove EEW from some sched classes.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 20 08:23:32 PDT 2022
Author: Craig Topper
Date: 2022-10-20T08:23:22-07:00
New Revision: c66426f3a06fa8626b1bd4fb0844aa04a424037c
URL: https://github.com/llvm/llvm-project/commit/c66426f3a06fa8626b1bd4fb0844aa04a424037c
DIFF: https://github.com/llvm/llvm-project/commit/c66426f3a06fa8626b1bd4fb0844aa04a424037c.diff
LOG: [RISCV] Remove EEW from some sched classes.
This removes the EEW from unit stride load/store and whole register
load, store, move.
It seems reasonable that implementations of these instructions wouldn't
usually be affected by element width.
We likely need to add LMUL information to our scheduling classes so
I thought it might be good to remove a few before they got multiplied
by LMUL.
Reviewed By: reames, michaelmaitland
Differential Revision: https://reviews.llvm.org/D135992
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index ea22a888d8bd3..65e36e0aa3b8c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -101,12 +101,9 @@ def simm5_plus1_nonzero : ImmLeaf<XLenVT,
class VMVRSched<int n>: Sched <[!cast<SchedReadWrite>("WriteVMov" # n # "V"),
!cast<SchedReadWrite>("ReadVMov" # n # "V")]>;
-class VLESched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDE" # n),
- ReadVLDX, ReadVMask]>;
+class VLESched : Sched <[WriteVLDE, ReadVLDX, ReadVMask]>;
-class VSESched<int n> : Sched <[!cast<SchedReadWrite>("WriteVSTE" # n),
- !cast<SchedReadWrite>("ReadVSTE" # n # "V"),
- ReadVSTX, ReadVMask]>;
+class VSESched : Sched <[WriteVSTE, ReadVSTEV, ReadVSTX, ReadVMask]>;
class VLSSched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDS" # n),
ReadVLDX, ReadVLDSX, ReadVMask]>;
@@ -124,15 +121,14 @@ class VSXSched<int n, string o> :
!cast<SchedReadWrite>("ReadVST" # o # "X" # n),
ReadVSTX, !cast<SchedReadWrite>("ReadVST" # o # "XV"), ReadVMask]>;
-class VLFSched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDFF" # n),
- ReadVLDX, ReadVMask]>;
+class VLFSched : Sched <[WriteVLDFF, ReadVLDX, ReadVMask]>;
// Unit-Stride Segment Loads and Stores
class VLSEGSched<int nf, int eew> : Sched<[
!cast<SchedReadWrite>("WriteVLSEG" #nf #"e" #eew), ReadVLDX, ReadVMask]>;
class VSSEGSched<int nf, int eew> : Sched<[
- !cast<SchedReadWrite>("WriteVSSEG" #nf #"e" #eew),
- !cast<SchedReadWrite>("ReadVSTE" #eew #"V"), ReadVSTX, ReadVMask]>;
+ !cast<SchedReadWrite>("WriteVSSEG" #nf #"e" #eew), ReadVSTEV, ReadVSTX,
+ ReadVMask]>;
class VLSEGFFSched<int nf, int eew> : Sched<[
!cast<SchedReadWrite>("WriteVLSEGFF" #nf #"e" #eew), ReadVLDX, ReadVMask]>;
// Strided Segment Loads and Stores
@@ -821,7 +817,7 @@ multiclass VCPR_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
multiclass VWholeLoadN<bits<3> nf, string opcodestr, RegisterClass VRC> {
foreach l = [8, 16, 32] in {
defvar w = !cast<RISCVWidth>("LSWidth" # l);
- defvar s = !cast<SchedWrite>("WriteVLD" # !add(nf, 1) # "R" # l);
+ defvar s = !cast<SchedWrite>("WriteVLD" # !add(nf, 1) # "R");
def E # l # _V : VWholeLoad<nf, w, opcodestr # "e" # l # ".v", VRC>,
Sched<[s, ReadVLDX]>;
@@ -853,11 +849,11 @@ foreach eew = [8, 16, 32] in {
defvar w = !cast<RISCVWidth>("LSWidth" # eew);
// Vector Unit-Stride Instructions
- def VLE#eew#_V : VUnitStrideLoad<w, "vle"#eew#".v">, VLESched<eew>;
- def VSE#eew#_V : VUnitStrideStore<w, "vse"#eew#".v">, VSESched<eew>;
+ def VLE#eew#_V : VUnitStrideLoad<w, "vle"#eew#".v">, VLESched;
+ def VSE#eew#_V : VUnitStrideStore<w, "vse"#eew#".v">, VSESched;
// Vector Unit-Stride Fault-only-First Loads
- def VLE#eew#FF_V : VUnitStrideLoadFF<w, "vle"#eew#"ff.v">, VLFSched<eew>;
+ def VLE#eew#FF_V : VUnitStrideLoadFF<w, "vle"#eew#"ff.v">, VLFSched;
// Vector Strided Instructions
def VLSE#eew#_V : VStridedLoad<w, "vlse"#eew#".v">, VLSSched<eew>;
@@ -900,13 +896,13 @@ def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>;
let Predicates = [HasVInstructionsI64] in {
// Vector Unit-Stride Instructions
def VLE64_V : VUnitStrideLoad<LSWidth64, "vle64.v">,
- VLESched<64>;
+ VLESched;
def VLE64FF_V : VUnitStrideLoadFF<LSWidth64, "vle64ff.v">,
- VLFSched<64>;
+ VLFSched;
def VSE64_V : VUnitStrideStore<LSWidth64, "vse64.v">,
- VSESched<64>;
+ VSESched;
// Vector Strided Instructions
def VLSE64_V : VStridedLoad<LSWidth64, "vlse64.v">,
VLSSched<32>;
@@ -914,10 +910,10 @@ def VLSE64_V : VStridedLoad<LSWidth64, "vlse64.v">,
def VSSE64_V : VStridedStore<LSWidth64, "vsse64.v">,
VSSSched<64>;
-defm VL1R: VWholeLoadEEW64<0, "vl1r", VR, WriteVLD1R64>;
-defm VL2R: VWholeLoadEEW64<1, "vl2r", VRM2, WriteVLD2R64>;
-defm VL4R: VWholeLoadEEW64<3, "vl4r", VRM4, WriteVLD4R64>;
-defm VL8R: VWholeLoadEEW64<7, "vl8r", VRM8, WriteVLD8R64>;
+defm VL1R: VWholeLoadEEW64<0, "vl1r", VR, WriteVLD1R>;
+defm VL2R: VWholeLoadEEW64<1, "vl2r", VRM2, WriteVLD2R>;
+defm VL4R: VWholeLoadEEW64<3, "vl4r", VRM4, WriteVLD4R>;
+defm VL8R: VWholeLoadEEW64<7, "vl8r", VRM8, WriteVLD8R>;
} // Predicates = [HasVInstructionsI64]
let Predicates = [IsRV64, HasVInstructionsI64] in {
// Vector Indexed Instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 49034c583fc9a..7c765dd3548bc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1607,14 +1607,14 @@ multiclass VPseudoUSLoad {
let VLMul = lmul.value in {
def "E" # eew # "_V_" # LInfo :
VPseudoUSLoadNoMask<vreg, eew>,
- VLESched<eew>;
+ VLESched;
def "E" # eew # "_V_" # LInfo # "_TU":
VPseudoUSLoadNoMaskTU<vreg, eew>,
- VLESched<eew>;
+ VLESched;
def "E" # eew # "_V_" # LInfo # "_MASK" :
VPseudoUSLoadMask<vreg, eew>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
- VLESched<eew>;
+ VLESched;
}
}
}
@@ -1628,14 +1628,14 @@ multiclass VPseudoFFLoad {
let VLMul = lmul.value in {
def "E" # eew # "FF_V_" # LInfo:
VPseudoUSLoadFFNoMask<vreg, eew>,
- VLFSched<eew>;
+ VLFSched;
def "E" # eew # "FF_V_" # LInfo # "_TU":
VPseudoUSLoadFFNoMaskTU<vreg, eew>,
- VLFSched<eew>;
+ VLFSched;
def "E" # eew # "FF_V_" # LInfo # "_MASK":
VPseudoUSLoadFFMask<vreg, eew>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
- VLFSched<eew>;
+ VLFSched;
}
}
}
@@ -1708,9 +1708,9 @@ multiclass VPseudoUSStore {
defvar vreg = lmul.vrclass;
let VLMul = lmul.value in {
def "E" # eew # "_V_" # LInfo : VPseudoUSStoreNoMask<vreg, eew>,
- VSESched<eew>;
+ VSESched;
def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg, eew>,
- VSESched<eew>;
+ VSESched;
}
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index df0a34fd29c3f..3c5b48803f4c4 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -19,14 +19,8 @@ def WriteVSETVL : SchedWrite;
// 7. Vector Loads and Stores
// 7.4. Vector Unit-Stride Instructions
-def WriteVLDE8 : SchedWrite;
-def WriteVLDE16 : SchedWrite;
-def WriteVLDE32 : SchedWrite;
-def WriteVLDE64 : SchedWrite;
-def WriteVSTE8 : SchedWrite;
-def WriteVSTE16 : SchedWrite;
-def WriteVSTE32 : SchedWrite;
-def WriteVSTE64 : SchedWrite;
+def WriteVLDE : SchedWrite;
+def WriteVSTE : SchedWrite;
// 7.4.1. Vector Unit-Strided Mask
def WriteVLDM : SchedWrite;
def WriteVSTM : SchedWrite;
@@ -57,10 +51,7 @@ def WriteVSTOX16 : SchedWrite;
def WriteVSTOX32 : SchedWrite;
def WriteVSTOX64 : SchedWrite;
// 7.7. Vector Unit-stride Fault-Only-First Loads
-def WriteVLDFF8 : SchedWrite;
-def WriteVLDFF16 : SchedWrite;
-def WriteVLDFF32 : SchedWrite;
-def WriteVLDFF64 : SchedWrite;
+def WriteVLDFF : SchedWrite;
// 7.8. Vector Segment Instructions
foreach nf=2-8 in {
foreach eew = [8, 16, 32, 64] in {
@@ -76,22 +67,10 @@ foreach nf=2-8 in {
}
}
// 7.9. Vector Whole Register Instructions
-def WriteVLD1R8 : SchedWrite;
-def WriteVLD1R16 : SchedWrite;
-def WriteVLD1R32 : SchedWrite;
-def WriteVLD1R64 : SchedWrite;
-def WriteVLD2R8 : SchedWrite;
-def WriteVLD2R16 : SchedWrite;
-def WriteVLD2R32 : SchedWrite;
-def WriteVLD2R64 : SchedWrite;
-def WriteVLD4R8 : SchedWrite;
-def WriteVLD4R16 : SchedWrite;
-def WriteVLD4R32 : SchedWrite;
-def WriteVLD4R64 : SchedWrite;
-def WriteVLD8R8 : SchedWrite;
-def WriteVLD8R16 : SchedWrite;
-def WriteVLD8R32 : SchedWrite;
-def WriteVLD8R64 : SchedWrite;
+def WriteVLD1R : SchedWrite;
+def WriteVLD2R : SchedWrite;
+def WriteVLD4R : SchedWrite;
+def WriteVLD8R : SchedWrite;
def WriteVST1R : SchedWrite;
def WriteVST2R : SchedWrite;
def WriteVST4R : SchedWrite;
@@ -284,10 +263,7 @@ def ReadVSETVL : SchedRead;
def ReadVLDX : SchedRead;
def ReadVSTX : SchedRead;
// 7.4. Vector Unit-Stride Instructions
-def ReadVSTE8V : SchedRead;
-def ReadVSTE16V : SchedRead;
-def ReadVSTE32V : SchedRead;
-def ReadVSTE64V : SchedRead;
+def ReadVSTEV : SchedRead;
// 7.4.1. Vector Unit-Strided Mask
def ReadVSTM : SchedRead;
// 7.5. Vector Strided Instructions
@@ -513,14 +489,8 @@ def : WriteRes<WriteVSETIVLI, []>;
def : WriteRes<WriteVSETVL, []>;
// 7. Vector Loads and Stores
-def : WriteRes<WriteVLDE8, []>;
-def : WriteRes<WriteVLDE16, []>;
-def : WriteRes<WriteVLDE32, []>;
-def : WriteRes<WriteVLDE64, []>;
-def : WriteRes<WriteVSTE8, []>;
-def : WriteRes<WriteVSTE16, []>;
-def : WriteRes<WriteVSTE32, []>;
-def : WriteRes<WriteVSTE64, []>;
+def : WriteRes<WriteVLDE, []>;
+def : WriteRes<WriteVSTE, []>;
def : WriteRes<WriteVLDM, []>;
def : WriteRes<WriteVSTM, []>;
def : WriteRes<WriteVLDS8, []>;
@@ -547,26 +517,11 @@ def : WriteRes<WriteVSTOX8, []>;
def : WriteRes<WriteVSTOX16, []>;
def : WriteRes<WriteVSTOX32, []>;
def : WriteRes<WriteVSTOX64, []>;
-def : WriteRes<WriteVLDFF8, []>;
-def : WriteRes<WriteVLDFF16, []>;
-def : WriteRes<WriteVLDFF32, []>;
-def : WriteRes<WriteVLDFF64, []>;
-def : WriteRes<WriteVLD1R8, []>;
-def : WriteRes<WriteVLD1R16, []>;
-def : WriteRes<WriteVLD1R32, []>;
-def : WriteRes<WriteVLD1R64, []>;
-def : WriteRes<WriteVLD2R8, []>;
-def : WriteRes<WriteVLD2R16, []>;
-def : WriteRes<WriteVLD2R32, []>;
-def : WriteRes<WriteVLD2R64, []>;
-def : WriteRes<WriteVLD4R8, []>;
-def : WriteRes<WriteVLD4R16, []>;
-def : WriteRes<WriteVLD4R32, []>;
-def : WriteRes<WriteVLD4R64, []>;
-def : WriteRes<WriteVLD8R8, []>;
-def : WriteRes<WriteVLD8R16, []>;
-def : WriteRes<WriteVLD8R32, []>;
-def : WriteRes<WriteVLD8R64, []>;
+def : WriteRes<WriteVLDFF, []>;
+def : WriteRes<WriteVLD1R, []>;
+def : WriteRes<WriteVLD2R, []>;
+def : WriteRes<WriteVLD4R, []>;
+def : WriteRes<WriteVLD8R, []>;
def : WriteRes<WriteVST1R, []>;
def : WriteRes<WriteVST2R, []>;
def : WriteRes<WriteVST4R, []>;
@@ -712,10 +667,7 @@ def : ReadAdvance<ReadVSETVL, 0>;
// 7. Vector Loads and Stores
def : ReadAdvance<ReadVLDX, 0>;
def : ReadAdvance<ReadVSTX, 0>;
-def : ReadAdvance<ReadVSTE8V, 0>;
-def : ReadAdvance<ReadVSTE16V, 0>;
-def : ReadAdvance<ReadVSTE32V, 0>;
-def : ReadAdvance<ReadVSTE64V, 0>;
+def : ReadAdvance<ReadVSTEV, 0>;
def : ReadAdvance<ReadVSTM, 0>;
def : ReadAdvance<ReadVLDSX, 0>;
def : ReadAdvance<ReadVSTSX, 0>;
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