[PATCH] D135567: [AArch64] SME2 Multiple vectors int/float binary accumulator and two/four ZA single-vector

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td:289
 defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>;
+
 }
----------------
nit: whitespace


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1367
+                                      RegisterOperand vector_ty>
+    : sme2_multivec_accum_add_sub<mnemonic,sz, is_int, s,
+                                  matrix_ty, vector_ty , "vgx2"> {
----------------
nit: Perhaps insert a space before `sz`?


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1377
+  def NAME : sme2_multivec_accum_add_sub_vg2<mnemonic, 0b0, op{1}, op{0},
+                                                     MatrixOp32, ZZ_s_mul_r>;
+
----------------
nit: Can you align this with `mnemonic` above?


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1385
+  def NAME : sme2_multivec_accum_add_sub_vg2<mnemonic, 0b1, op{1}, op{0},
+                                                     MatrixOp64, ZZ_d_mul_r>;
+  def : InstAlias<mnemonic # "\t$ZAdn[$Rv, $imm3], $Zm",
----------------
nit: Alignment


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1404
+  def NAME : sme2_multivec_accum_add_sub_vg4<mnemonic, 0b0, op{1}, op{0},
+                                                     MatrixOp32, ZZZZ_s_mul_r>;
+
----------------
nit: Alignment


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1412
+  def NAME : sme2_multivec_accum_add_sub_vg4<mnemonic, 0b1, op{1}, op{0},
+                                                     MatrixOp64, ZZZZ_d_mul_r>;
+  def : InstAlias<mnemonic # "\t$ZAdn[$Rv, $imm3], $Zm",
----------------
nit: Alignment


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1473
 
+
----------------
nit: whitespace


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Comment at: llvm/test/MC/AArch64/SME2/add.s:41
+add     za.s[w8, 0, vgx2], {z0.s-z1.s}  // 11000001-10100000-00011100-00010000
+// CHECK-INST: add     za.s[w8, 0, vgx2], { z0.s-z1.s }
+// CHECK-ENCODING: [0x10,0x1c,0xa0,0xc1]
----------------
Is this output still correct? I was expecting the vector list to be printed out as `{ z0.s, z1.s }`. Perhaps this patch just needs a rebase?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135567/new/

https://reviews.llvm.org/D135567