[PATCH] D135957: [AArch64][SeperateConstOffsetFromGEP] Prevent pass from splitting GEP if an index has more than one use

[Zain Jaffal via Phabricator via llvm-commits]

zjaffal added a comment.

In D135957#3864526 <https://reviews.llvm.org/D135957#3864526>, @zjaffal wrote:

>> There is a RISCV test that is failing.
>
> I checked that out and the pass is correct for RISCV. I am thinking of moving this to be handled in AArch64 backend instead.

Correction, I think splitting is also worse for RISCV:
This is the failing test case for RISCV

  define i64 @test1(i64* %array, i64 %i, i64 %j)  {
  
  entry:
    %add = add nsw i64 %i, 5
    %gep = getelementptr inbounds i64, i64* %array, i64 %add
    store i64 %j, i64* %gep
    %add2 = add nsw i64 %i, 6
    %gep2 = getelementptr inbounds i64, i64* %array, i64 %add2
    store i64 %j, i64* %gep2
    %add3 = add nsw i64 %i, 35
    %gep3 = getelementptr inbounds i64, i64* %array, i64 %add3
    store i64 %add, i64* %gep3
    ret i64 undef
  }

Splitting generates the following IR

  addi    a3, a1, 5
  slli    a4, a3, 3
  add     a4, a0, a4
  srli    a5, a2, 32
  sw      a5, 4(a4)
  sw      a2, 0(a4)
  slli    a1, a1, 3
  add     a0, a1, a0
  sw      a5, 52(a0)
  sw      a2, 48(a0)
  sw      a3, 280(a0)
  srli    a1, a3, 32
  sw      a1, 284(a0)
  ret

While disabling the pass generates

  addi    a3, a1, 5
  slli    a4, a3, 3
  add     a4, a0, a4
  sd      a2, 0(a4)
  slli    a1, a1, 3
  add     a0, a1, a0
  sd      a2, 48(a0)
  sd      a3, 280(a0)
  ret

Which contains fewer instructions.


Repository:
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