[llvm] 0f4dc56 - [LoongArch] Fix 32-bit and 64-bit atomicrmw nand operand order errors

[via llvm-commits]

Author: gonglingqin
Date: 2022-10-20T17:26:33+08:00
New Revision: 0f4dc562bca3ad61bfc194b9e435c5b27f219461

URL: https://github.com/llvm/llvm-project/commit/0f4dc562bca3ad61bfc194b9e435c5b27f219461
DIFF: https://github.com/llvm/llvm-project/commit/0f4dc562bca3ad61bfc194b9e435c5b27f219461.diff

LOG: [LoongArch] Fix 32-bit and 64-bit atomicrmw nand operand order errors

Differential Revision: https://reviews.llvm.org/D136220

Added: 
    

Modified: 
    llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
    llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index 880070846429a..2c1aa3aca68ad 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -1194,7 +1194,7 @@ def : Pat<(atomic_load_sub_64 GPR:$rj, GPR:$rk),
 def : AtomicPat<int_loongarch_masked_atomicrmw_sub_i64,
                 PseudoMaskedAtomicLoadSub32>;
 def : Pat<(atomic_load_nand_64 GPR:$rj, GPR:$rk),
-          (PseudoAtomicLoadNand64 GPR:$rk, GPR:$rj)>;
+          (PseudoAtomicLoadNand64 GPR:$rj, GPR:$rk)>;
 def : AtomicPat<int_loongarch_masked_atomicrmw_nand_i64,
                 PseudoMaskedAtomicLoadNand32>;
 def : Pat<(atomic_load_add_32 GPR:$rj, GPR:$rk),
@@ -1228,7 +1228,7 @@ def : AtomicPat<int_loongarch_masked_atomicrmw_umin_i64,
 } // Predicates = [IsLA64]
 
 def : Pat<(atomic_load_nand_32 GPR:$rj, GPR:$rk),
-          (PseudoAtomicLoadNand32 GPR:$rk, GPR:$rj)>;
+          (PseudoAtomicLoadNand32 GPR:$rj, GPR:$rk)>;
 
 let Predicates = [IsLA32] in {
 def : AtomicPat<int_loongarch_masked_atomicrmw_xchg_i32,

diff  --git a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
index 0a50abfd8bf8f..cc96c165edc01 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
@@ -547,10 +547,10 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
 ; LA32:       # %bb.0:
 ; LA32-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
 ; LA32-NEXT:    dbar 0
-; LA32-NEXT:    ll.w $a2, $a1, 0
-; LA32-NEXT:    and $a3, $a2, $a0
+; LA32-NEXT:    ll.w $a2, $a0, 0
+; LA32-NEXT:    and $a3, $a2, $a1
 ; LA32-NEXT:    nor $a3, $a3, $zero
-; LA32-NEXT:    sc.w $a3, $a1, 0
+; LA32-NEXT:    sc.w $a3, $a0, 0
 ; LA32-NEXT:    beqz $a3, .LBB14_1
 ; LA32-NEXT:  # %bb.2:
 ; LA32-NEXT:    move $a0, $a2
@@ -560,10 +560,10 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
 ; LA64:       # %bb.0:
 ; LA64-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    ll.w $a2, $a1, 0
-; LA64-NEXT:    and $a3, $a2, $a0
+; LA64-NEXT:    ll.w $a2, $a0, 0
+; LA64-NEXT:    and $a3, $a2, $a1
 ; LA64-NEXT:    nor $a3, $a3, $zero
-; LA64-NEXT:    sc.w $a3, $a1, 0
+; LA64-NEXT:    sc.w $a3, $a0, 0
 ; LA64-NEXT:    beqz $a3, .LBB14_1
 ; LA64-NEXT:  # %bb.2:
 ; LA64-NEXT:    move $a0, $a2
@@ -587,10 +587,10 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind {
 ; LA64:       # %bb.0:
 ; LA64-NEXT:  .LBB15_1: # =>This Inner Loop Header: Depth=1
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    ll.d $a2, $a1, 0
-; LA64-NEXT:    and $a3, $a2, $a0
+; LA64-NEXT:    ll.d $a2, $a0, 0
+; LA64-NEXT:    and $a3, $a2, $a1
 ; LA64-NEXT:    nor $a3, $a3, $zero
-; LA64-NEXT:    sc.d $a3, $a1, 0
+; LA64-NEXT:    sc.d $a3, $a0, 0
 ; LA64-NEXT:    beqz $a3, .LBB15_1
 ; LA64-NEXT:  # %bb.2:
 ; LA64-NEXT:    move $a0, $a2