[PATCH] D134277: [RISCV] Combine comparison and logic ops.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8313
+  // Condition 1. Operations have to have same value type.
+  if (V0.getValueType() != V1.getValueType())
+    return None;
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This is required by the definition of ISD::AND/OR. It can be an assert.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8324
+
+  // SETCC has three operands: op0, op1, cond. Checks only the first two.
+  // Returns Iterator to condition operand in comparison.
----------------
I'm not sure the std::finds and std::distance added much over manually checking the 4 permutations.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8365
+  // If common operand at the first position then swap operation to convert to
+  // strict patternt. Common operand has to be right hand side.
+  ISD::CondCode RefCond = cast<CondCodeSDNode>(*GetCmpIt(V0))->get();
----------------
pattern*


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8395
+  // Condition 4. Compare operands has to be the same type.
+  if (A.getValueType() != B.getValueType() ||
+      A.getValueType() != C.getValueType())
----------------
If the compares a common operand, then all of the operands must be the same type.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134277/new/

https://reviews.llvm.org/D134277