[PATCH] D135753: [VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll:1170
+; RV64-NEXT:    vmax.vx v8, v8, a0, v0.t
+; RV64-NEXT:    vsetivli zero, 0, e32, m8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v24
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fakepaper56 wrote:
> craig.topper wrote:
> > Why does RV64 not see the EVL is 0?
> As the comment of the test illustrated,  DAGCombiner could not transformed `usubsat((and (vscale x 16), 0xffffffff), vscale x 16)` to 0 before lowering. And vp binary operations are only existed before lowering.
Thanks. I didn't see the comment.


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  https://reviews.llvm.org/D135753/new/

https://reviews.llvm.org/D135753