[PATCH] D136236: [AMDGPU][GISel] Allow VReg srcs in (build_vector undef, i16) pattern

Wed Oct 19 11:47:19 PDT 2022

arsenm added inline comments.

================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:2740-2741
 def : GCNPat <
-  (v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 SReg_32:$src1))),
+  (v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 VS_32:$src1))),
   (v2i16 (V_LSHLREV_B32_e64 (i32 16), SReg_32:$src1))
 >;
----------------
foad wrote:
> arsenm wrote:
> > foad wrote:
> > > Why does this pattern use SReg_32? That doesn't make any sense to me.
> > The output should change to match.
> > 
> > It makes sense for the old DAG select everything to scalar and hack up to vector later approach 
> Well I still don't get why it ever made sense. I know we used to select SALU instructions by default, but this is a VALU instruction with an SGPR operand. I thought we always used VGPR operands by default for VALU instructions, to avoid having to think about constant bus restrictions until SIFoldOperands.
The register class in the pattern used to mean less and was practically an alias for the type. There was a finalize ISel hook to fixup constant bus violations 

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  https://reviews.llvm.org/D136236/new/

https://reviews.llvm.org/D136236