[PATCH] D124325: [AArch64][SVE] Support logical operation BIC with DestructiveBinary patterns

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp:592
+  // Zeros the lanes in z0 that aren't active in p0 with sequence movprfx
+  // z0.b, p0/z, z0.b; add z0.b, z0.b, #0;
+  if (DType == AArch64::DestructiveBinary &&
----------------
paulwalker-arm wrote:
> Do any of the tests exercise this code?
I don't believe this is safe because only predicated instructions are allowed to follow a predicated `movprfx` instruction. There's a section within
```
https://developer.arm.com/documentation/ddi0487/latest/

Data processing - SVE
-> Move operations
--> Move prefix
```
that details which instructions are allowed to follow a `movprfx`. 


================
Comment at: llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp:592-600
+  // z0.b, p0/z, z0.b; add z0.b, z0.b, #0;
+  if (DType == AArch64::DestructiveBinary &&
+      DstReg == MI.getOperand(SrcIdx).getReg()) {
+    ADD = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AddZero))
+              .addReg(DstReg, RegState::Define)
+              .addReg(DstReg)
+              .addImm(0)
----------------
Do any of the tests exercise this code?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124325/new/

https://reviews.llvm.org/D124325