[llvm] f0ca946 - [AMDGPU] New helper function SIInsertWaitcnts::getVmemWaitEventType
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 19 08:32:58 PDT 2022
Author: Jay Foad
Date: 2022-10-19T16:22:50+01:00
New Revision: f0ca946bf917430bc97f80a5791312ef28c48320
URL: https://github.com/llvm/llvm-project/commit/f0ca946bf917430bc97f80a5791312ef28c48320
DIFF: https://github.com/llvm/llvm-project/commit/f0ca946bf917430bc97f80a5791312ef28c48320.diff
LOG: [AMDGPU] New helper function SIInsertWaitcnts::getVmemWaitEventType
This just commons up and simplifies some logic that was repeated in
SIInsertWaitcnts::updateEventWaitcntAfter. NFCI.
Differential Revision: https://reviews.llvm.org/D136253
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 0f9f1aee8996..5b352ac7b870 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -434,6 +434,17 @@ class SIInsertWaitcnts : public MachineFunctionPass {
#endif // NDEBUG
}
+ // Return the appropriate VMEM_*_ACCESS type for Inst, which must be a VMEM or
+ // FLAT instruction.
+ WaitEventType getVmemWaitEventType(const MachineInstr &Inst) const {
+ assert(SIInstrInfo::isVMEM(Inst) || SIInstrInfo::isFLAT(Inst));
+ if (!ST->hasVscnt())
+ return VMEM_ACCESS;
+ if (Inst.mayStore() && !SIInstrInfo::isAtomicRet(Inst))
+ return VMEM_WRITE_ACCESS;
+ return VMEM_READ_ACCESS;
+ }
+
bool mayAccessVMEMThroughFlat(const MachineInstr &MI) const;
bool mayAccessLDSThroughFlat(const MachineInstr &MI) const;
bool generateWaitcntInstBefore(MachineInstr &MI,
@@ -1384,12 +1395,8 @@ void SIInsertWaitcnts::updateEventWaitcntAfter(MachineInstr &Inst,
if (mayAccessVMEMThroughFlat(Inst)) {
++FlatASCount;
- if (!ST->hasVscnt())
- ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_ACCESS, Inst);
- else if (Inst.mayLoad() && !SIInstrInfo::isAtomicNoRet(Inst))
- ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_READ_ACCESS, Inst);
- else
- ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_WRITE_ACCESS, Inst);
+ ScoreBrackets->updateByEvent(TII, TRI, MRI, getVmemWaitEventType(Inst),
+ Inst);
}
if (mayAccessLDSThroughFlat(Inst)) {
@@ -1407,14 +1414,8 @@ void SIInsertWaitcnts::updateEventWaitcntAfter(MachineInstr &Inst,
ScoreBrackets->setPendingFlat();
} else if (SIInstrInfo::isVMEM(Inst) &&
!llvm::AMDGPU::getMUBUFIsBufferInv(Inst.getOpcode())) {
- if (!ST->hasVscnt())
- ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_ACCESS, Inst);
- else if ((Inst.mayLoad() && !SIInstrInfo::isAtomicNoRet(Inst)) ||
- /* IMAGE_GET_RESINFO / IMAGE_GET_LOD */
- (TII->isMIMG(Inst) && !Inst.mayLoad() && !Inst.mayStore()))
- ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_READ_ACCESS, Inst);
- else if (Inst.mayStore())
- ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_WRITE_ACCESS, Inst);
+ ScoreBrackets->updateByEvent(TII, TRI, MRI, getVmemWaitEventType(Inst),
+ Inst);
if (ST->vmemWriteNeedsExpWaitcnt() &&
(Inst.mayStore() || SIInstrInfo::isAtomicRet(Inst))) {
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