[PATCH] D135563: [AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:1091
     DecoderMethod = "DecodeZPR2Mul2RegisterClass" in {
+  def ZZ_b_mul_r : RegisterOperand<ZPR2, "printTypedVectorList<0,'b'>"> {
+    let ParserMatchClass = ZPRVectorListMul<8, 2>;
----------------
sdesmalen wrote:
> Using ZPR2 here (and ZPR4 for ZZZZ_b_mul_r) isn't correct.
> 
> ZPR2 allows:
>   {z0.b, z1.b}
>   {z1.b, z2.b}
>   {z2.b, z3.b}
>   {z3.b, z4.b}
>   ...
> 
> But `{z1.b, z2.b}` and `{z3.b, z4.b}` are not valid for ZZ_b_mul_r, because the first register must be a multiple of 2.
> 
> To fix this, you can create a new register class that only takes the "even" pairs (for ZPR2) or every fourth quad (for ZPR4) like this:
> 
>   // SME2 multiple-of-2 or 4 multi-vector operands
>   def ZPR2Mul2 : RegisterClass<"AArch64", [untyped], 128, (add (decimate ZSeqPairs, 2))> {
>     let Size = 256;
>   }
>   
>   def ZPR4Mul4 : RegisterClass<"AArch64", [untyped], 128, (add (decimate ZSeqQuads, 4))> {
>     let Size = 512;
>   }
> 
This makes sense, although the diagnostics tests do show that we correctly reject registers starting at non-multiples I think? Not sure why this works - perhaps the ParserMatchClass takes care of it?


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  https://reviews.llvm.org/D135563/new/

https://reviews.llvm.org/D135563