[PATCH] D136238: [AMDGPU] Assume getDefIgnoringCopies will succeed. NFC.
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 19 02:34:39 PDT 2022
foad created this revision.
foad added reviewers: AMDGPU, arsenm, Pierre-vh.
Herald added subscribers: kosarev, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, jvesely, kzhuravl.
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foad requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.
getDefIgnoringCopies and getSrcRegIgnoringCopies should not fail on
valid MIR, so don't bother to check for failure.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D136238
Files:
llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Index: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -674,7 +674,7 @@
// TODO: This should probably be a combine somewhere
// (build_vector $src0, undef) -> copy $src0
MachineInstr *Src1Def = getDefIgnoringCopies(Src1, *MRI);
- if (Src1Def && Src1Def->getOpcode() == AMDGPU::G_IMPLICIT_DEF) {
+ if (Src1Def->getOpcode() == AMDGPU::G_IMPLICIT_DEF) {
MI.setDesc(TII.get(AMDGPU::COPY));
MI.removeOperand(2);
const auto &RC =
@@ -1451,8 +1451,6 @@
return false;
MachineInstr *OffsetDef = getDefIgnoringCopies(BaseOffset, *MRI);
- assert(OffsetDef);
-
unsigned ImmOffset;
MachineBasicBlock *MBB = MI.getParent();
@@ -3036,7 +3034,7 @@
} else if (AddrDef->MI->getOpcode() == AMDGPU::G_PTR_ADD) {
Register SAddr =
getSrcRegIgnoringCopies(AddrDef->MI->getOperand(1).getReg(), *MRI);
- if (SAddr && isSGPR(SAddr)) {
+ if (isSGPR(SAddr)) {
Register PtrBaseOffset = AddrDef->MI->getOperand(2).getReg();
if (Register Off = matchZeroExtendFromS32(*MRI, PtrBaseOffset)) {
Addr = SAddr;
@@ -3330,13 +3328,13 @@
unsigned Mods = 0;
MachineInstr *MI = getDefIgnoringCopies(Src, *MRI);
- if (MI && MI->getOpcode() == AMDGPU::G_FNEG) {
+ if (MI->getOpcode() == AMDGPU::G_FNEG) {
Src = MI->getOperand(1).getReg();
Mods |= SISrcMods::NEG;
MI = getDefIgnoringCopies(Src, *MRI);
}
- if (AllowAbs && MI && MI->getOpcode() == AMDGPU::G_FABS) {
+ if (AllowAbs && MI->getOpcode() == AMDGPU::G_FABS) {
Src = MI->getOperand(1).getReg();
Mods |= SISrcMods::ABS;
}
@@ -3436,8 +3434,7 @@
AMDGPUInstructionSelector::selectVOP3NoMods(MachineOperand &Root) const {
Register Reg = Root.getReg();
const MachineInstr *Def = getDefIgnoringCopies(Reg, *MRI);
- if (Def && (Def->getOpcode() == AMDGPU::G_FNEG ||
- Def->getOpcode() == AMDGPU::G_FABS))
+ if (Def->getOpcode() == AMDGPU::G_FNEG || Def->getOpcode() == AMDGPU::G_FABS)
return {};
return {{
[=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); },
@@ -3826,7 +3823,7 @@
Register SAddr =
getSrcRegIgnoringCopies(AddrDef->MI->getOperand(1).getReg(), *MRI);
- if (SAddr && isSGPR(SAddr)) {
+ if (isSGPR(SAddr)) {
Register PtrBaseOffset = AddrDef->MI->getOperand(2).getReg();
// It's possible voffset is an SGPR here, but the copy to VGPR will be
Index: llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
@@ -20,9 +20,6 @@
AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
GISelKnownBits *KnownBits) {
MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
- if (!Def)
- return std::make_pair(Reg, 0);
-
if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
unsigned Offset;
const MachineOperand &Op = Def->getOperand(1);
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