[PATCH] D136172: [AArch64]SME2 Multi vector Sel instructions
Caroline via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 18 07:09:49 PDT 2022
CarolineConcatto created this revision.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
CarolineConcatto requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
This patch adds the assembly/disassembly for the following instruction:
SEL: Multi-vector conditionally select elements from two vectors.
for 2 and 4 registers
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
This patch also adds a new register class Predicate-as-counter (PN)
PNRP8_15RegOp
The predicate register AArch64:P<x> is used as a predicate-as-count
register Pn<x>[idx].
To represent that (P<x> predicate as Pn<x>[idx] predicate as a counter) this
patch creates a new AsmOperand class PNRAsmOperand.
PRNAsmOperand inherits from PPRAsmOperand but with a new predicate method. The new
predicate method checks if the register operand is the new Register Kind
SMEPredicateAsCounter.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D136172
Files:
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
llvm/lib/Target/AArch64/SMEInstrFormats.td
llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
llvm/test/MC/AArch64/SME2/sel-diagnostics.s
llvm/test/MC/AArch64/SME2/sel.s
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