[PATCH] D136042: [DAG] Enable combineShiftOfShiftedLogic folds after type legalization

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D136042#3864932 <https://reviews.llvm.org/D136042#3864932>, @RKSimon wrote:

> @foad What do you think about the AMDGPU diffs? Do you want me to focus on getting D136081 <https://reviews.llvm.org/D136081> done first?

The diffs look OK to me, modulo one pretty minor regression noted inline.

As for the general approach of putting the smarts in `AMDGPUTargetLowering::isDesirableToCommuteWithShift`: does AMDGPU have special code to match `or(shl(load_zext(),c), load_zext())` and merge it into a wider load? If so, could it be improved to match the case where both loads are shifted? On the other hand, since you've already coded and tested this approach, I think it is fine.



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Comment at: llvm/test/CodeGen/AMDGPU/sdiv.ll:1652
-; GCN-NEXT:    v_or_b32_e32 v1, v2, v1
-; GCN-NEXT:    v_bfe_i32 v1, v1, 0, 23
-; GCN-NEXT:    v_cvt_f32_i32_e32 v2, v1
----------------
Seems like we are losing a couple of bfe formations here, and D136081 does not fix it.


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  https://reviews.llvm.org/D136042/new/

https://reviews.llvm.org/D136042