[llvm] 9572406 - [LoongArch] Fix codegen of atomicrmw nand

[Weining Lu via llvm-commits]

Author: Weining Lu
Date: 2022-10-18T20:39:20+08:00
New Revision: 9572406bbcb497f8c23c28daa762b55ee3219f41

URL: https://github.com/llvm/llvm-project/commit/9572406bbcb497f8c23c28daa762b55ee3219f41
DIFF: https://github.com/llvm/llvm-project/commit/9572406bbcb497f8c23c28daa762b55ee3219f41.diff

LOG: [LoongArch] Fix codegen of atomicrmw nand

Fix invalid RISCV-like MI being emitted for performing the `not`
operation: the LoongArch `xori` zero-extends the immediate, hence is
not equivalent to RISCV `xori`. The LoongArch `not` is a `nor` with
zero.

Differential Revision: https://reviews.llvm.org/D136021

Added: 
    

Modified: 
    llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
    llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
index 59cb615a02401..803e02f258dc1 100644
--- a/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
@@ -162,9 +162,9 @@ static void doAtomicBinOpExpansion(const LoongArchInstrInfo *TII,
     BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg)
         .addReg(DestReg)
         .addReg(IncrReg);
-    BuildMI(LoopMBB, DL, TII->get(LoongArch::XORI), ScratchReg)
+    BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg)
         .addReg(ScratchReg)
-        .addImm(-1);
+        .addReg(LoongArch::R0);
     break;
   case AtomicRMWInst::Add:
     BuildMI(LoopMBB, DL, TII->get(LoongArch::ADD_W), ScratchReg)
@@ -268,9 +268,9 @@ static void doMaskedAtomicBinOpExpansion(
     BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg)
         .addReg(DestReg)
         .addReg(IncrReg);
-    BuildMI(LoopMBB, DL, TII->get(LoongArch::XORI), ScratchReg)
+    BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg)
         .addReg(ScratchReg)
-        .addImm(-1);
+        .addReg(LoongArch::R0);
     // TODO: support other AtomicRMWInst.
   }
 

diff  --git a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
index 9761a402f9433..0a50abfd8bf8f 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
@@ -450,7 +450,7 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind {
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a4, $a2, 0
 ; LA32-NEXT:    and $a5, $a4, $a1
-; LA32-NEXT:    xori $a5, $a5, -1
+; LA32-NEXT:    nor $a5, $a5, $zero
 ; LA32-NEXT:    xor $a5, $a4, $a5
 ; LA32-NEXT:    and $a5, $a5, $a3
 ; LA32-NEXT:    xor $a5, $a4, $a5
@@ -475,7 +475,7 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind {
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.w $a4, $a2, 0
 ; LA64-NEXT:    and $a5, $a4, $a1
-; LA64-NEXT:    xori $a5, $a5, -1
+; LA64-NEXT:    nor $a5, $a5, $zero
 ; LA64-NEXT:    xor $a5, $a4, $a5
 ; LA64-NEXT:    and $a5, $a5, $a3
 ; LA64-NEXT:    xor $a5, $a4, $a5
@@ -503,7 +503,7 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind {
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a4, $a2, 0
 ; LA32-NEXT:    and $a5, $a4, $a1
-; LA32-NEXT:    xori $a5, $a5, -1
+; LA32-NEXT:    nor $a5, $a5, $zero
 ; LA32-NEXT:    xor $a5, $a4, $a5
 ; LA32-NEXT:    and $a5, $a5, $a3
 ; LA32-NEXT:    xor $a5, $a4, $a5
@@ -529,7 +529,7 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind {
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.w $a4, $a2, 0
 ; LA64-NEXT:    and $a5, $a4, $a1
-; LA64-NEXT:    xori $a5, $a5, -1
+; LA64-NEXT:    nor $a5, $a5, $zero
 ; LA64-NEXT:    xor $a5, $a4, $a5
 ; LA64-NEXT:    and $a5, $a5, $a3
 ; LA64-NEXT:    xor $a5, $a4, $a5
@@ -549,7 +549,7 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a2, $a1, 0
 ; LA32-NEXT:    and $a3, $a2, $a0
-; LA32-NEXT:    xori $a3, $a3, -1
+; LA32-NEXT:    nor $a3, $a3, $zero
 ; LA32-NEXT:    sc.w $a3, $a1, 0
 ; LA32-NEXT:    beqz $a3, .LBB14_1
 ; LA32-NEXT:  # %bb.2:
@@ -562,7 +562,7 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.w $a2, $a1, 0
 ; LA64-NEXT:    and $a3, $a2, $a0
-; LA64-NEXT:    xori $a3, $a3, -1
+; LA64-NEXT:    nor $a3, $a3, $zero
 ; LA64-NEXT:    sc.w $a3, $a1, 0
 ; LA64-NEXT:    beqz $a3, .LBB14_1
 ; LA64-NEXT:  # %bb.2:
@@ -589,7 +589,7 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind {
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.d $a2, $a1, 0
 ; LA64-NEXT:    and $a3, $a2, $a0
-; LA64-NEXT:    xori $a3, $a3, -1
+; LA64-NEXT:    nor $a3, $a3, $zero
 ; LA64-NEXT:    sc.d $a3, $a1, 0
 ; LA64-NEXT:    beqz $a3, .LBB15_1
 ; LA64-NEXT:  # %bb.2: