[PATCH] D136021: [LoongArch] Fix codegen of atomicrmw nand

[Lu Weining via Phabricator via llvm-commits]

SixWeining updated this revision to Diff 468501.
SixWeining added a comment.

update test case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136021/new/

https://reviews.llvm.org/D136021

Files:
  llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
  llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll


Index: llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
===================================================================
--- llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
+++ llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
@@ -450,7 +450,7 @@
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a4, $a2, 0
 ; LA32-NEXT:    and $a5, $a4, $a1
-; LA32-NEXT:    xori $a5, $a5, -1
+; LA32-NEXT:    nor $a5, $a5, $zero
 ; LA32-NEXT:    xor $a5, $a4, $a5
 ; LA32-NEXT:    and $a5, $a5, $a3
 ; LA32-NEXT:    xor $a5, $a4, $a5
@@ -475,7 +475,7 @@
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.w $a4, $a2, 0
 ; LA64-NEXT:    and $a5, $a4, $a1
-; LA64-NEXT:    xori $a5, $a5, -1
+; LA64-NEXT:    nor $a5, $a5, $zero
 ; LA64-NEXT:    xor $a5, $a4, $a5
 ; LA64-NEXT:    and $a5, $a5, $a3
 ; LA64-NEXT:    xor $a5, $a4, $a5
@@ -503,7 +503,7 @@
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a4, $a2, 0
 ; LA32-NEXT:    and $a5, $a4, $a1
-; LA32-NEXT:    xori $a5, $a5, -1
+; LA32-NEXT:    nor $a5, $a5, $zero
 ; LA32-NEXT:    xor $a5, $a4, $a5
 ; LA32-NEXT:    and $a5, $a5, $a3
 ; LA32-NEXT:    xor $a5, $a4, $a5
@@ -529,7 +529,7 @@
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.w $a4, $a2, 0
 ; LA64-NEXT:    and $a5, $a4, $a1
-; LA64-NEXT:    xori $a5, $a5, -1
+; LA64-NEXT:    nor $a5, $a5, $zero
 ; LA64-NEXT:    xor $a5, $a4, $a5
 ; LA64-NEXT:    and $a5, $a5, $a3
 ; LA64-NEXT:    xor $a5, $a4, $a5
@@ -549,7 +549,7 @@
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a2, $a1, 0
 ; LA32-NEXT:    and $a3, $a2, $a0
-; LA32-NEXT:    xori $a3, $a3, -1
+; LA32-NEXT:    nor $a3, $a3, $zero
 ; LA32-NEXT:    sc.w $a3, $a1, 0
 ; LA32-NEXT:    beqz $a3, .LBB14_1
 ; LA32-NEXT:  # %bb.2:
@@ -562,7 +562,7 @@
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.w $a2, $a1, 0
 ; LA64-NEXT:    and $a3, $a2, $a0
-; LA64-NEXT:    xori $a3, $a3, -1
+; LA64-NEXT:    nor $a3, $a3, $zero
 ; LA64-NEXT:    sc.w $a3, $a1, 0
 ; LA64-NEXT:    beqz $a3, .LBB14_1
 ; LA64-NEXT:  # %bb.2:
@@ -589,7 +589,7 @@
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.d $a2, $a1, 0
 ; LA64-NEXT:    and $a3, $a2, $a0
-; LA64-NEXT:    xori $a3, $a3, -1
+; LA64-NEXT:    nor $a3, $a3, $zero
 ; LA64-NEXT:    sc.d $a3, $a1, 0
 ; LA64-NEXT:    beqz $a3, .LBB15_1
 ; LA64-NEXT:  # %bb.2:
Index: llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
===================================================================
--- llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
+++ llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
@@ -162,9 +162,9 @@
     BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg)
         .addReg(DestReg)
         .addReg(IncrReg);
-    BuildMI(LoopMBB, DL, TII->get(LoongArch::XORI), ScratchReg)
+    BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg)
         .addReg(ScratchReg)
-        .addImm(-1);
+        .addReg(LoongArch::R0);
     break;
   case AtomicRMWInst::Add:
     BuildMI(LoopMBB, DL, TII->get(LoongArch::ADD_W), ScratchReg)
@@ -268,9 +268,9 @@
     BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg)
         .addReg(DestReg)
         .addReg(IncrReg);
-    BuildMI(LoopMBB, DL, TII->get(LoongArch::XORI), ScratchReg)
+    BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg)
         .addReg(ScratchReg)
-        .addImm(-1);
+        .addReg(LoongArch::R0);
     // TODO: support other AtomicRMWInst.
   }
 


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