[PATCH] D136157: [X86][2/2] Support PREFETCHI instructions

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:36838
+    unsigned Opc =
+        MI.getOpcode() == X86::PREFETCHIT0 ? X86::PREFETCHT0 : X86::PREFETCHT1;
+    if (MI.getOperand(0).getReg() != X86::RIP) {
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It seems morph code prefetch to data prefetch. Does it help performance? I'm sure about the cache hierarchy. Which cache level is shared between code cache and data cache?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136157/new/

https://reviews.llvm.org/D136157