[PATCH] D136150: [AArch64]SME2 Single and Multi vector Shift and Multiply instructions

[Caroline via Phabricator via llvm-commits]

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This patch adds the assembly/disassembly for the following instructions:

  SQDMULH (multiple vectors): Multi-vector signed saturating doubling multiply high.
  SQRSHR (four registers): Multi-vector signed saturating rounding shift right narrow by immediate.
         (two registers): Multi-vector signed saturating rounding shift right narrow by immediate.
  SQRSHRN: Multi-vector signed saturating rounding shift right narrow by immediate and interleave.
  SQRSHRU (four registers): Multi-vector signed saturating rounding shift right unsigned narrow by immediate.
          (two registers): Multi-vector signed saturating rounding shift right unsigned narrow by immediate.
  SQRSHRUN: Multi-vector signed saturating rounding shift right unsigned narrow by immediate and interleave.
  SRSHL (multiple and single vector): Multi-vector signed rounding shift left by vector.
        (multiple vectors): Multi-vector signed rounding shift left.
  UQRSHR (four registers): Multi-vector unsigned saturating rounding shift right narrow by immediate
         (two registers): Multi-vector unsigned saturating rounding shift right narrow by immediate.
  UQRSHRN: Multi-vector unsigned saturating rounding shift right narrow by immediate and interleave.
  URSHL (multiple and single vector): Multi-vector unsigned rounding shift left by vector.
        (multiple vectors): Multi-vector unsigned rounding shift left.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136150

Files:
  llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
  llvm/lib/Target/AArch64/SMEInstrFormats.td
  llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s
  llvm/test/MC/AArch64/SME2/sqdmulh.s
  llvm/test/MC/AArch64/SME2/sqrshr-diagnostics.s
  llvm/test/MC/AArch64/SME2/sqrshr.s
  llvm/test/MC/AArch64/SME2/sqrshrn-diagnostics.s
  llvm/test/MC/AArch64/SME2/sqrshrn.s
  llvm/test/MC/AArch64/SME2/sqrshru-diagnostics.s
  llvm/test/MC/AArch64/SME2/sqrshru.s
  llvm/test/MC/AArch64/SME2/sqrshrun-diagnostics.s
  llvm/test/MC/AArch64/SME2/sqrshrun.s
  llvm/test/MC/AArch64/SME2/srshl-diagnostics.s
  llvm/test/MC/AArch64/SME2/srshl.s
  llvm/test/MC/AArch64/SME2/uqrshr-diagnostics.s
  llvm/test/MC/AArch64/SME2/uqrshr.s
  llvm/test/MC/AArch64/SME2/uqrshrn-diagnostics.s
  llvm/test/MC/AArch64/SME2/uqrshrn.s
  llvm/test/MC/AArch64/SME2/urshl-diagnostics.s
  llvm/test/MC/AArch64/SME2/urshl.s

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