[PATCH] D136051: [CodeGen] Introduce a flag to allow same cycle def-use schedule

[David Penry via Phabricator via llvm-commits]

dpenry added a comment.

The test in isValidSchedule isn't there to prevent use/def in the same cycle due to assumed limitations in targets; in general, we do want to allow use/def in the same cycle if that's what the scheduling model has led us to.  Instead, it's there to work around misoptimizations caused by the fact that while orderDependence is responsible for making sure that use/def are properly ordered within a single cycle, orderDependence doesn't attempt to do so when physical registers are involved.

So I worry that Hexagon working when the test is elided is simply a happy side-effect of its current scheduling models, and not due to a guarantee that def/use ordering cannot somehow get violated when modulo scheduling is performed for it.  Of course, before I added the test, Hexagon was presumably not having problems, so maybe there is something special about it, in which case this change seems reasonable -- though perhaps with a commit message with a bit more explanation (e.g. that this only affects physical registers).

I do think a more robust solution, likely also improving scheduling for multiple targets, would be to get orderDependence to properly handle def/use ordering when there's a physical register, though I don't know how difficult that might be.  I'm adding the (assumed) original author of orderDependence to the reviewer list to see if they have more insight.


Repository:
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https://reviews.llvm.org/D136051