[PATCH] D136040: [X86] Support PREFETCHI instructions

[Phoebe Wang via Phabricator via llvm-commits]

pengfei updated this revision to Diff 468195.
pengfei added subscribers: uweigand, t.p.northover.
pengfei added a comment.

1. Address review comments;
2. Optimize prefetchit0/1 to prefetcht0/1 for non-rip address;
3. Add semacheck for prefetch write to instruction cache;
4. Fix a bug that set `rw` = 1 for prefetchit0/1;

I think the affected ARM and SystemZ tests are not valid before. Could @t.p.northover and @uweigand help to have a look?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136040/new/

https://reviews.llvm.org/D136040

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/prfchiintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/prefetchi-builtins.c
  clang/test/CodeGen/builtins-arm.c
  clang/test/Driver/x86-target-features.c
  clang/test/Sema/builtin-prefetch.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/IR/Verifier.cpp
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86Instr3DNow.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/SystemZ/prefetch-01.ll
  llvm/test/CodeGen/X86/prefetch.ll
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/PREFETCH-64.s

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