[PATCH] D136059: [AMDGPU][DAG] Fix trunc/shift combine condition
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 17 02:43:05 PDT 2022
foad added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3255-3256
+ const unsigned MaxCstSize = (Src.getOpcode() == ISD::SHL)
+ ? Size
+ : (32 - VT.getScalarSizeInBits());
+ if ((Known.isConstant() && Known.getConstant().ule(MaxCstSize)) ||
----------------
For left shifts you can do it so long as the new shift amount is still valid, so ShiftAmt < 32 (aka <= 31).
So this can be: `... ? 31 : 32 - Size`
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3258
+ if ((Known.isConstant() && Known.getConstant().ule(MaxCstSize)) ||
(Known.countMaxActiveBits() <= Log2_32(Size))) {
EVT MidVT = VT.isVector() ?
----------------
The whole `if` condition can be replaced with: `Known.getMaxValue().ule(MaxCstSize)`
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D136059/new/
https://reviews.llvm.org/D136059
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