[PATCH] D135991: [AArch64] Fix cost model for `udiv` instruction when one of the operands is a uniform constant

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:2059
     if (Ty->isVectorTy()) {
+      // if one of the operands is a uniform constant then the cost for each
+      // element is Cost for insertion, extraction and division.
----------------
I think this is broken because you're assuming that all vectors are of type FixedVectorType. This code will crash if you one of the operands is a constant and we're dealing with scalable vector types. Perhaps it's better to move this to the else case below, i.e.

  if (TLI->isOperationLegalOrCustom(ISD, LT.second) && ST->hasSVE()) {
    ...
  } else {
    if ((Op1Info.isConstant() && Op1Info.isUniform()) ||
      ...
    // On AArch64, without SVE, vector divisions are expanded

We shouldn't be dealing with scalable vectors at this point so the `cast<FixedVectorType>(Ty)` ought to be fine.


================
Comment at: llvm/test/Analysis/CostModel/AArch64/div.ll:181
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %I64 = sdiv i64 undef, 7
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %V2i64 = sdiv <2 x i64> undef, <i64 7, i64 7>
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %V4i64 = sdiv <4 x i64> undef, <i64 7, i64 7, i64 7, i64 7>
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 192 for instruction: %V8i64 = sdiv <8 x i64> undef, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V2i64 = sdiv <2 x i64> undef, <i64 7, i64 7>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V4i64 = sdiv <4 x i64> undef, <i64 7, i64 7, i64 7, i64 7>
----------------
dmgreen wrote:
> It seems odd that doing 2 divides, plus some cross-register-bank copies, would be cheaper than doing 1
I agree with @dmgreen, this does look odd.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135991/new/

https://reviews.llvm.org/D135991