[PATCH] D136042: [DAG] Enable combineShiftOfShiftedLogic folds after type legalization

[Simon Pilgrim via Phabricator via llvm-commits]

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This was disabled to prevent regressions, which appear to be just occuring on AMDGPU (at least in our current lit tests).

I think I've addressed most of them by adding a AMDGPU isDesirableToCommuteWithShift override - with just a missing 'sign-extend-in-reg' BFE fold for (ashr(or(shl(x,c1), shl(y,c2)),c1) which needs to addressed seperately: https://gcc.godbolt.org/z/qnzP7KKad

Fixes #57872


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136042

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
  llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
  llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
  llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
  llvm/test/CodeGen/AMDGPU/sdiv.ll
  llvm/test/CodeGen/BPF/pr57872.ll
  llvm/test/CodeGen/Mips/cconv/return-struct.ll
  llvm/test/CodeGen/Mips/cconv/vector.ll
  llvm/test/CodeGen/Mips/load-store-left-right.ll
  llvm/test/CodeGen/Mips/unalignedload.ll
  llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/unaligned-load-store.ll
  llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
  llvm/test/CodeGen/Thumb/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/X86/bool-vector.ll
  llvm/test/CodeGen/X86/combine-bitreverse.ll
  llvm/test/CodeGen/X86/is_fpclass.ll
  llvm/test/CodeGen/X86/vector-sext.ll

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