[PATCH] D135951: [X86] SUPPORT RAO-INT

Sat Oct 15 20:09:07 PDT 2022

pengfei added inline comments.

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Comment at: llvm/lib/Target/X86/X86.td:259
+                                     "Support RAO-INT instructions",
+                                     [FeatureSSE2]>;
 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
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craig.topper wrote:
> Why do these require SSE2?
We need mfence instructions for strong orders. The mfence feature relies on SSE2.
I see your concern, we may need split these features from SSE2. Filed an issue https://github.com/llvm/llvm-project/issues/58388

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Comment at: llvm/lib/Target/X86/X86ISelLowering.h:801
+    RXOR,
+    RAND,
+
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craig.topper wrote:
> RKSimon wrote:
> > very pedantic, but are these likely to get confused with ROR / RAND instructions? Would it be better to use a RAO_ prefix?
> Why not AADD etc to match the instruction names?
Good ideas, thanks!

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Comment at: llvm/test/CodeGen/X86/atomic-instructions-32.ll:5
+; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64-NO-RAOINT
+; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+raoint | FileCheck %s --check-prefixes=X64-RAO-INT
+
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RKSimon wrote:
> Is the -O0 necessary?
I missed that, thanks!

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135951/new/

https://reviews.llvm.org/D135951