[PATCH] D135992: [RISCV] Remove EEW from some sched clases.

[Craig Topper via Phabricator via llvm-commits]

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This removes the EEW from unit stride load/store and whole register
load, store, move.

It seems reasonable that implementations of these instructions wouldn't
usually be affected by element width.

We likely need to add LMUL information to our scheduling classes so
I thought it might be good to remove a few before they got multiplied
by LMUL.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135992

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

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