[llvm] 1fab0ac - [RISCV] Rename ReadVIALUCV->ReadVICALUV to match WriteVICALUV. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 14 12:14:39 PDT 2022
Author: Craig Topper
Date: 2022-10-14T12:11:55-07:00
New Revision: 1fab0ac559a1eb4e74d193c772264b590ad3c317
URL: https://github.com/llvm/llvm-project/commit/1fab0ac559a1eb4e74d193c772264b590ad3c317
DIFF: https://github.com/llvm/llvm-project/commit/1fab0ac559a1eb4e74d193c772264b590ad3c317.diff
LOG: [RISCV] Rename ReadVIALUCV->ReadVICALUV to match WriteVICALUV. NFC
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 06dda660f154..ea22a888d8bd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -460,11 +460,11 @@ multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6> {
def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
def IM : VALUmVI<funct6, opcodestr # ".vim">,
- Sched<[WriteVICALUI, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUI, ReadVICALUV, ReadVMask]>;
}
multiclass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> {
@@ -478,25 +478,25 @@ multiclass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> {
multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
}
multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5> {
def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV]>;
def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX]>;
def I : VALUVINoVm<funct6, opcodestr # ".vi", optype>,
- Sched<[WriteVICALUI, ReadVIALUCV]>;
+ Sched<[WriteVICALUI, ReadVICALUV]>;
}
multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV]>;
def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX]>;
}
multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index fefcf60d39c1..49034c583fc9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2496,62 +2496,62 @@ multiclass VPseudoVMRG_VM_XM_IM {
multiclass VPseudoVCALU_VM_XM_IM {
defm "" : VPseudoBinaryV_VM,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
defm "" : VPseudoBinaryV_XM,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
defm "" : VPseudoBinaryV_IM,
- Sched<[WriteVICALUI, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUI, ReadVICALUV, ReadVMask]>;
// Tied versions to allow codegen control over the tail elements
defm "" : VPseudoTiedBinaryV_VM,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
defm "" : VPseudoTiedBinaryV_XM,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
defm "" : VPseudoTiedBinaryV_IM,
- Sched<[WriteVICALUI, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUI, ReadVICALUV, ReadVMask]>;
}
multiclass VPseudoVCALU_VM_XM {
defm "" : VPseudoBinaryV_VM,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
defm "" : VPseudoBinaryV_XM,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
// Tied versions to allow codegen control over the tail elements
defm "" : VPseudoTiedBinaryV_VM,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
defm "" : VPseudoTiedBinaryV_XM,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
}
multiclass VPseudoVCALUM_VM_XM_IM<string Constraint> {
defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
defm "" : VPseudoBinaryV_IM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
- Sched<[WriteVICALUI, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUI, ReadVICALUV, ReadVMask]>;
}
multiclass VPseudoVCALUM_VM_XM<string Constraint> {
defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
}
multiclass VPseudoVCALUM_V_X_I<string Constraint> {
defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV]>;
defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX]>;
defm "" : VPseudoBinaryV_IM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
- Sched<[WriteVICALUI, ReadVIALUCV]>;
+ Sched<[WriteVICALUI, ReadVICALUV]>;
}
multiclass VPseudoVCALUM_V_X<string Constraint> {
defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
- Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV]>;
+ Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV]>;
defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
- Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX]>;
+ Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX]>;
}
multiclass VPseudoVNCLP_WV_WX_WI {
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 7b43be5c5b0d..df0a34fd29c3 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -335,8 +335,8 @@ def ReadVIWALUX : SchedRead;
// 11.3. Vector Integer Extension
def ReadVExtV : SchedRead;
// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions
-def ReadVIALUCV : SchedRead;
-def ReadVIALUCX : SchedRead;
+def ReadVICALUV : SchedRead;
+def ReadVICALUX : SchedRead;
// 11.6. Vector Single-Width Bit Shift Instructions
def ReadVShiftV : SchedRead;
def ReadVShiftX : SchedRead;
@@ -754,8 +754,8 @@ def : ReadAdvance<ReadVIALUX, 0>;
def : ReadAdvance<ReadVIWALUV, 0>;
def : ReadAdvance<ReadVIWALUX, 0>;
def : ReadAdvance<ReadVExtV, 0>;
-def : ReadAdvance<ReadVIALUCV, 0>;
-def : ReadAdvance<ReadVIALUCX, 0>;
+def : ReadAdvance<ReadVICALUV, 0>;
+def : ReadAdvance<ReadVICALUX, 0>;
def : ReadAdvance<ReadVShiftV, 0>;
def : ReadAdvance<ReadVShiftX, 0>;
def : ReadAdvance<ReadVNShiftV, 0>;
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