[PATCH] D135952: [AArch64]Change printVectorList to print SVE vector range

Fri Oct 14 09:25:05 PDT 2022

CarolineConcatto marked 3 inline comments as done.
CarolineConcatto added inline comments.

================
Comment at: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp:1472
     O << LayoutSuffix;
-
-    if (i + 1 != NumRegs)
-      O << ", ";
+    if (NumRegs > 1) {
+      // Set of two sve registers should be separated by ','
----------------
sdesmalen wrote:
> There should be a fallback to the comma-separated form if the registers are not consecutive, for example when the register wraps as in:
> 
>   ld4b  { z29.b, z30.b, z31.b, z0.b }, p0/z, [x0, x0]
> 
> This should remain a comma-separated list.
> 
> It would also be good to have a test for this, in case it doesn't exist yet.
I have added at least one test for st3/st4 and ld3/l4

================
Comment at: llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s:2569
 # CHECK-NEXT:  1      1     0.50                        addvl	x23, x8, #-1
-# CHECK-NEXT:  2      5     2.00                        adr	z0.d, [z0.d, z0.d, lsl #1]
-# CHECK-NEXT:  2      5     2.00                        adr	z0.d, [z0.d, z0.d, lsl #2]
-# CHECK-NEXT:  2      5     2.00                        adr	z0.d, [z0.d, z0.d, lsl #3]
-# CHECK-NEXT:  1      4     0.50                        adr	z0.d, [z0.d, z0.d, sxtw #1]
-# CHECK-NEXT:  1      4     0.50                        adr	z0.d, [z0.d, z0.d, sxtw #2]
-# CHECK-NEXT:  1      4     0.50                        adr	z0.d, [z0.d, z0.d, sxtw #3]
+# CHECK-NEXT:  2      5     2.00                        adr	z0.d, [z0.d, z0.d, lsl  #1]
+# CHECK-NEXT:  2      5     2.00                        adr	z0.d, [z0.d, z0.d, lsl  #2]
----------------
sdesmalen wrote:
> These whitespace changes should not be here.
I removed the white spaces, but it was added by update_mca_test_checks.py.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135952/new/

https://reviews.llvm.org/D135952