[PATCH] D135024: [PowerPC] Fix invalid cast for vector shuffles when lowering to the xxsplti32dx instruction.

Fri Oct 14 08:57:11 PDT 2022

amyk added inline comments.

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Comment at: llvm/test/CodeGen/PowerPC/p10-splatImm32-undef.ll:35-60
+; CHECK-AIX-NEXT:    stxv vs52, 112(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs53, 128(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs54, 144(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs55, 160(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs56, 176(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs57, 192(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs58, 208(r1) # 16-byte Folded Spill
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nemanjai wrote:
> ZarkoCA wrote:
> > These register spills are not seen with any other target in the test case. Is this maybe an artifact of the test case, or something else? What happens on Linux 64 BE? 
> Seems unrelated to this patch but nonetheless it is bad. @amyk can you please pre-commit the test case?
@ZarkoCA @nemanjai Good catch! Thanks, both of you. 

So, I've pre-committed the test case with 64-bit Linux (LE and BE) and AIX lines initially. I could not add the 32-bit run lines since they crash (and this patch aims to fix the 32-bit crash). 

As we can see with the 64-bit CHECKs, the spills aren't present anymore and they don't seem to be related to my patch, so maybe there was something causing it before that got fixed?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135024/new/

https://reviews.llvm.org/D135024