[PATCH] D135952: [AArch64]Change printVectorList to print SVE vector range

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp:1469
 
-  for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
-    if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
-      printRegName(O, Reg);
-    else
-      printRegName(O, Reg, AArch64::vreg);
+  if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg)) {
+    printRegName(O, Reg);
----------------
We should be doing the same for NEON, but I'm happy for that to happen in a different patch.


================
Comment at: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp:1472
     O << LayoutSuffix;
-
-    if (i + 1 != NumRegs)
-      O << ", ";
+    if (NumRegs > 1) {
+      // Set of two sve registers should be separated by ','
----------------
There should be a fallback to the comma-separated form if the registers are not consecutive, for example when the register wraps as in:

  ld4b  { z29.b, z30.b, z31.b, z0.b }, p0/z, [x0, x0]

This should remain a comma-separated list.

It would also be good to have a test for this, in case it doesn't exist yet.


================
Comment at: llvm/test/CodeGen/AArch64/sve-merging-stores.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
----------------
This test doesn't need changing at all now that it remains a comma-separated vector list.


================
Comment at: llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s:2569
 # CHECK-NEXT:  1      1     0.50                        addvl	x23, x8, #-1
-# CHECK-NEXT:  2      5     2.00                        adr	z0.d, [z0.d, z0.d, lsl #1]
-# CHECK-NEXT:  2      5     2.00                        adr	z0.d, [z0.d, z0.d, lsl #2]
-# CHECK-NEXT:  2      5     2.00                        adr	z0.d, [z0.d, z0.d, lsl #3]
-# CHECK-NEXT:  1      4     0.50                        adr	z0.d, [z0.d, z0.d, sxtw #1]
-# CHECK-NEXT:  1      4     0.50                        adr	z0.d, [z0.d, z0.d, sxtw #2]
-# CHECK-NEXT:  1      4     0.50                        adr	z0.d, [z0.d, z0.d, sxtw #3]
+# CHECK-NEXT:  2      5     2.00                        adr	z0.d, [z0.d, z0.d, lsl  #1]
+# CHECK-NEXT:  2      5     2.00                        adr	z0.d, [z0.d, z0.d, lsl  #2]
----------------
These whitespace changes should not be here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135952/new/

https://reviews.llvm.org/D135952