[PATCH] D135954: [DAGCombiner] Fix crash for the merge stores with different value type

Fri Oct 14 02:48:52 PDT 2022

bcl5980 created this revision.
bcl5980 added reviewers: RKSimon, craig.topper, spatel, efriedma.
Herald added subscribers: StephenFan, ecnelises, hiraditya.
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bcl5980 requested review of this revision.
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Herald added a subscriber: llvm-commits.

The crash case comes from #58350. It have two stores, one store is type f32 and the other is v1f32.
When we try to merge these two stores on v1f32, the memVT is vector type so the old code will use ISD::EXTRACT_SUBVECTOR for type f32 also then compiler crash.
So this patch insert a build_vector for f32 store to generate v1f32 also when memVT is v1f32.


https://reviews.llvm.org/D135954

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/dag-combine-store-merge.ll


Index: llvm/test/CodeGen/AArch64/dag-combine-store-merge.ll
===================================================================

--- /dev/null
+++ llvm/test/CodeGen/AArch64/dag-combine-store-merge.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+
+; This used to hit an assertion like this:
+; llc: /llvm_path/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:6366: llvm::SDValue llvm::SelectionDAG::getNode(unsigned int, const llvm::SDLoc &, llvm::EVT, llvm::SDValue, llvm::SDValue, const llvm::SDNodeFlags): Assertion `N2C && "Extract subvector index must be a constant"' failed.
+; PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
+; Stack dump:
+; 0.	Program arguments: ./llvm-project/build-debug/bin/llc ./crash-reports/dagisel-aarch64/1.ll -mtriple=aarch64
+; 1.	Running pass 'Function Pass Manager' on module './crash-reports/dagisel-aarch64/1.ll'.
+; 2.	Running pass 'AArch64 Instruction Selection' on function '@f'
+;  #0 0x0000000003af78fa llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /llvm_path/llvm-project/llvm/lib/Support/Unix/Signals.inc:569:11
+;  #1 0x0000000003af7aab PrintStackTraceSignalHandler(void*) /llvm_path/llvm-project/llvm/lib/Support/Unix/Signals.inc:636:1
+;  #2 0x0000000003af60f6 llvm::sys::RunSignalHandlers() /llvm_path/llvm-project/llvm/lib/Support/Signals.cpp:104:5
+;  #3 0x0000000003af81d5 SignalHandler(int) /llvm_path/llvm-project/llvm/lib/Support/Unix/Signals.inc:407:1
+;  #4 0x00007f614194c980 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x12980)
+;  #5 0x00007f614083ce87 raise /build/glibc-uZu3wS/glibc-2.27/signal/../sysdeps/unix/sysv/linux/raise.c:51:0
+;  #6 0x00007f614083e7f1 abort /build/glibc-uZu3wS/glibc-2.27/stdlib/abort.c:81:0
+;  #7 0x00007f614082e3fa __assert_fail_base /build/glibc-uZu3wS/glibc-2.27/assert/assert.c:89:0
+;  #8 0x00007f614082e472 (/lib/x86_64-linux-gnu/libc.so.6+0x30472)
+;  #9 0x0000000003800507 llvm::SelectionDAG::getNode(unsigned int, llvm::SDLoc const&, llvm::EVT, llvm::SDValue, llvm::SDValue, llvm::SDNodeFlags) /llvm_path/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:6367:5
+; #10 0x00000000037dbf90 llvm::SelectionDAG::getNode(unsigned int, llvm::SDLoc const&, llvm::EVT, llvm::SDValue, llvm::SDValue) /llvm_path/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5975:10
+; #11 0x00000000036b73d2 (anonymous namespace)::DAGCombiner::mergeStoresOfConstantsOrVecElts(llvm::SmallVectorImpl<(anonymous namespace)::DAGCombiner::MemOpLink>&, llvm::EVT, unsigned int, bool, bool, bool) /llvm_path/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:18329:23
+; #12 0x00000000036b209a (anonymous namespace)::DAGCombiner::tryStoreMergeOfExtracts(llvm::SmallVectorImpl<(anonymous namespace)::DAGCombiner::MemOpLink>&, unsigned int, llvm::EVT, llvm::SDNode*) /llvm_path/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:18866:19
+; #13 0x00000000036ac2f5 (anonymous namespace)::DAGCombiner::mergeConsecutiveStores(llvm::StoreSDNode*) /llvm_path/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:19229:21
+; #14 0x00000000036464e2 (anonymous namespace)::DAGCombiner::visitSTORE(llvm::SDNode*) /llvm_path/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:19538:12
+; #15 0x00000000035fd9a8 (anonymous namespace)::DAGCombiner::visit(llvm::SDNode*) /llvm_path/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1787:40
+; #16 0x00000000035fcae8 (anonymous namespace)::DAGCombiner::combine(llvm::SDNode*) /llvm_path/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1828:10
+
+define void @f(<1 x float> %a, i64 %b) {
+; CHECK-LABEL: f:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub sp, sp, #16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    adrp x8, .LCPI0_0
+; CHECK-NEXT:    and x9, x0, #0x1
+; CHECK-NEXT:    mov x10, sp
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI0_0]
+; CHECK-NEXT:    bfi x10, x9, #2, #1
+; CHECK-NEXT:    str d1, [sp]
+; CHECK-NEXT:    ldr s1, [x10]
+; CHECK-NEXT:    mov v1.s[1], v0.s[0]
+; CHECK-NEXT:    str d1, [sp, #8]
+; CHECK-NEXT:    add sp, sp, #16
+; CHECK-NEXT:    ret
+  %P = alloca i64
+  %E = extractelement <2 x float> <float 0.5, float 1.0>, i64 %b
+  %G = getelementptr <1 x float>, ptr %P, i64 1
+  store float %E, ptr %P
+  store <1 x float> %a, ptr %G
+  ret void
+}
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -18321,6 +18321,9 @@
           // We may need to add a bitcast here to get types to line up.
           if (MemVTScalarTy != Val.getValueType().getScalarType()) {
             Val = DAG.getBitcast(MemVT, Val);
+          } else if (MemVT.isVector() &&
+                     Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+            Val = DAG.getNode(ISD::BUILD_VECTOR, DL, MemVT, Val);
           } else {
             unsigned OpC = MemVT.isVector() ? ISD::EXTRACT_SUBVECTOR
                                             : ISD::EXTRACT_VECTOR_ELT;


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