[llvm] 0d253bb - [PowerPC] Change CRNOT to a code gen single operand instruction
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 13 18:09:58 PDT 2022
Author: Nemanja Ivanovic
Date: 2022-10-13T20:09:44-05:00
New Revision: 0d253bbd330020c005fff824771c4336622d0bfe
URL: https://github.com/llvm/llvm-project/commit/0d253bbd330020c005fff824771c4336622d0bfe
DIFF: https://github.com/llvm/llvm-project/commit/0d253bbd330020c005fff824771c4336622d0bfe.diff
LOG: [PowerPC] Change CRNOT to a code gen single operand instruction
Inputs to crnor can come from operands with chains so
if it is being used simply to negate such an operand,
the repeated input cannot be CSE'd. This patch just
adds a code-gen only instruction for this that takes
a single input and duplicates it in the encoding of
the underlying crnor.
Differential revision: https://reviews.llvm.org/D133577
Added:
Modified:
llvm/lib/Target/PowerPC/P10InstrResources.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCInstrFormats.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/P10InstrResources.td b/llvm/lib/Target/PowerPC/P10InstrResources.td
index a6ba5adda8394..232853635e0ae 100644
--- a/llvm/lib/Target/PowerPC/P10InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P10InstrResources.td
@@ -999,6 +999,7 @@ def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read],
CRANDC,
CRNAND,
CRNOR,
+ CRNOT,
CROR,
CRORC,
CR6UNSET, CRUNSET, CRXOR,
diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td
index 2bbab64ce0da4..ac20dd353c849 100644
--- a/llvm/lib/Target/PowerPC/P9InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -195,6 +195,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_3SLOTS_1C],
XSIEXPDP,
FMR,
CREQV,
+ CRNOT,
CRXOR,
TRECLAIM,
TSR,
diff --git a/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def b/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
index f1eecfea5a5e9..b8e9825621814 100644
--- a/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
+++ b/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
@@ -567,6 +567,7 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
CREQV,
CRNAND,
CRNOR,
+ CRNOT,
CROR,
CRORC,
CRSET,
@@ -1041,4 +1042,4 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
XXLXORdpz,
XXLXORspz,
XXLXORz,
- XXSEL))
\ No newline at end of file
+ XXSEL))
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 101e0b602f186..08349dac944c2 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -6571,8 +6571,9 @@ void PPCDAGToDAGISel::PeepholeCROps() {
Op2Set = true;
else if (Op.getMachineOpcode() == PPC::CRUNSET)
Op2Unset = true;
- else if (Op.getMachineOpcode() == PPC::CRNOR &&
- Op.getOperand(0) == Op.getOperand(1))
+ else if ((Op.getMachineOpcode() == PPC::CRNOR &&
+ Op.getOperand(0) == Op.getOperand(1)) ||
+ Op.getMachineOpcode() == PPC::CRNOT)
Op2Not = true;
}
[[fallthrough]];
@@ -6595,8 +6596,9 @@ void PPCDAGToDAGISel::PeepholeCROps() {
Op1Set = true;
else if (Op.getMachineOpcode() == PPC::CRUNSET)
Op1Unset = true;
- else if (Op.getMachineOpcode() == PPC::CRNOR &&
- Op.getOperand(0) == Op.getOperand(1))
+ else if ((Op.getMachineOpcode() == PPC::CRNOR &&
+ Op.getOperand(0) == Op.getOperand(1)) ||
+ Op.getMachineOpcode() == PPC::CRNOT)
Op1Not = true;
}
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index d4d7f1107b039..f0f8d6ebcf094 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -1411,6 +1411,13 @@ class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = 0;
}
+// XL-Form for unary alias for CRNOR (CRNOT)
+class XLForm_1s<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+ let CRB = CRA;
+}
+
class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 9fd8de484e5fb..ea4ef12bf21d2 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2481,13 +2481,17 @@ def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
(ins crbitrc:$CRA, crbitrc:$CRB),
"crnor $CRD, $CRA, $CRB", IIC_BrCR,
[(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
-
def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
(ins crbitrc:$CRA, crbitrc:$CRB),
"creqv $CRD, $CRA, $CRB", IIC_BrCR,
[(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
} // isCommutable
+let isCodeGenOnly = 1 in
+def CRNOT : XLForm_1s<19, 33, (outs crbitrc:$CRD), (ins crbitrc:$CRA),
+ "crnot $CRD, $CRA", IIC_BrCR,
+ [(set i1:$CRD, (not i1:$CRA))]>;
+
def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
(ins crbitrc:$CRA, crbitrc:$CRB),
"crandc $CRD, $CRA, $CRB", IIC_BrCR,
@@ -3267,7 +3271,7 @@ include "PPCInstrVSX.td"
include "PPCInstrHTM.td"
def crnot : OutPatFrag<(ops node:$in),
- (CRNOR $in, $in)>;
+ (CRNOT $in)>;
def : Pat<(not i1:$in),
(crnot $in)>;
diff --git a/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp b/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
index 5cee00c61fc1e..2ebbcc68f871b 100644
--- a/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
+++ b/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
@@ -390,9 +390,10 @@ class PPCReduceCRLogicals : public MachineFunctionPass {
static bool isCRLogical(MachineInstr &MI) {
unsigned Opc = MI.getOpcode();
return Opc == PPC::CRAND || Opc == PPC::CRNAND || Opc == PPC::CROR ||
- Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CREQV ||
- Opc == PPC::CRANDC || Opc == PPC::CRORC || Opc == PPC::CRSET ||
- Opc == PPC::CRUNSET || Opc == PPC::CR6SET || Opc == PPC::CR6UNSET;
+ Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CRNOT ||
+ Opc == PPC::CREQV || Opc == PPC::CRANDC || Opc == PPC::CRORC ||
+ Opc == PPC::CRSET || Opc == PPC::CRUNSET || Opc == PPC::CR6SET ||
+ Opc == PPC::CR6UNSET;
}
bool simplifyCode() {
bool Changed = false;
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
index d6e0ddea30f4a..9c84ef378149c 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
@@ -56,9 +56,7 @@ define i1 @test_f128(fp128 %a, fp128 %b) #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: crmove 4*cr5+lt, eq
-; CHECK-NEXT: xscmpuqp cr0, v2, v3
-; CHECK-NEXT: crmove 4*cr5+gt, eq
-; CHECK-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; CHECK-NEXT: crnot 4*cr5+lt, 4*cr5+lt
; CHECK-NEXT: li r4, 0
; CHECK-NEXT: li r3, 1
; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
index 86923667d912f..9d0d38a2b268c 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
@@ -30,13 +30,11 @@ define i32 @test_f32_ogt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_oge_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmplt cr0, r5, r6
-; SPE-NEXT: efscmplt cr1, r5, r6
-; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
; SPE-NEXT: efscmpeq cr0, r6, r6
; SPE-NEXT: efscmpeq cr1, r5, r5
-; SPE-NEXT: crand 4*cr5+gt, 4*cr1+gt, gt
-; SPE-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; SPE-NEXT: crand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT: efscmplt cr0, r5, r6
+; SPE-NEXT: crandc 4*cr5+lt, 4*cr5+lt, gt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
@@ -62,13 +60,11 @@ define i32 @test_f32_olt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_ole_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpgt cr0, r5, r6
-; SPE-NEXT: efscmpgt cr1, r5, r6
-; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
; SPE-NEXT: efscmpeq cr0, r6, r6
; SPE-NEXT: efscmpeq cr1, r5, r5
-; SPE-NEXT: crand 4*cr5+gt, 4*cr1+gt, gt
-; SPE-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; SPE-NEXT: crand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT: efscmpgt cr0, r5, r6
+; SPE-NEXT: crandc 4*cr5+lt, 4*cr5+lt, gt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
@@ -127,13 +123,9 @@ define i32 @test_f32_ueq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_ugt_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpeq cr0, r6, r6
-; SPE-NEXT: efscmpeq cr1, r6, r6
-; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
; SPE-NEXT: efscmpeq cr0, r5, r5
-; SPE-NEXT: efscmpeq cr1, r5, r5
-; SPE-NEXT: crnor 4*cr5+gt, gt, 4*cr1+gt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; SPE-NEXT: efscmpeq cr1, r6, r6
+; SPE-NEXT: crnand 4*cr5+lt, 4*cr1+gt, gt
; SPE-NEXT: efscmpgt cr0, r5, r6
; SPE-NEXT: cror 4*cr5+lt, gt, 4*cr5+lt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
@@ -149,11 +141,10 @@ define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_uge_s:
; SPE: # %bb.0:
; SPE-NEXT: efscmplt cr0, r5, r6
-; SPE-NEXT: efscmplt cr1, r5, r6
-; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
-; SPE-NEXT: # %bb.1:
-; SPE-NEXT: ori r3, r4, 0
+; SPE-NEXT: bc 12, gt, .LBB9_1
+; SPE-NEXT: blr
+; SPE-NEXT: .LBB9_1:
+; SPE-NEXT: addi r3, r4, 0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"uge", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -163,13 +154,9 @@ define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_ult_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpeq cr0, r6, r6
-; SPE-NEXT: efscmpeq cr1, r6, r6
-; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
; SPE-NEXT: efscmpeq cr0, r5, r5
-; SPE-NEXT: efscmpeq cr1, r5, r5
-; SPE-NEXT: crnor 4*cr5+gt, gt, 4*cr1+gt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; SPE-NEXT: efscmpeq cr1, r6, r6
+; SPE-NEXT: crnand 4*cr5+lt, 4*cr1+gt, gt
; SPE-NEXT: efscmplt cr0, r5, r6
; SPE-NEXT: cror 4*cr5+lt, gt, 4*cr5+lt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
@@ -185,11 +172,10 @@ define i32 @test_f32_ule_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_ule_s:
; SPE: # %bb.0:
; SPE-NEXT: efscmpgt cr0, r5, r6
-; SPE-NEXT: efscmpgt cr1, r5, r6
-; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
-; SPE-NEXT: # %bb.1:
-; SPE-NEXT: ori r3, r4, 0
+; SPE-NEXT: bc 12, gt, .LBB11_1
+; SPE-NEXT: blr
+; SPE-NEXT: .LBB11_1:
+; SPE-NEXT: addi r3, r4, 0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ule", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -200,11 +186,10 @@ define i32 @test_f32_une_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_une_s:
; SPE: # %bb.0:
; SPE-NEXT: efscmpeq cr0, r5, r6
-; SPE-NEXT: efscmpeq cr1, r5, r6
-; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
-; SPE-NEXT: # %bb.1:
-; SPE-NEXT: ori r3, r4, 0
+; SPE-NEXT: bc 12, gt, .LBB12_1
+; SPE-NEXT: blr
+; SPE-NEXT: .LBB12_1:
+; SPE-NEXT: addi r3, r4, 0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"une", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -214,13 +199,9 @@ define i32 @test_f32_une_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_uno_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_uno_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpeq cr0, r6, r6
-; SPE-NEXT: efscmpeq cr1, r6, r6
-; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
; SPE-NEXT: efscmpeq cr0, r5, r5
-; SPE-NEXT: efscmpeq cr1, r5, r5
-; SPE-NEXT: crnor 4*cr5+gt, gt, 4*cr1+gt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; SPE-NEXT: efscmpeq cr1, r6, r6
+; SPE-NEXT: crnand 4*cr5+lt, 4*cr1+gt, gt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
@@ -263,15 +244,13 @@ define i32 @test_f64_ogt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_oge_s:
; SPE: # %bb.0:
-; SPE-NEXT: evmergelo r7, r7, r8
; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmplt cr0, r5, r7
-; SPE-NEXT: efdcmplt cr1, r5, r7
-; SPE-NEXT: efdcmpeq cr5, r7, r7
-; SPE-NEXT: efdcmpeq cr6, r5, r5
-; SPE-NEXT: crnor 4*cr7+lt, gt, 4*cr1+gt
-; SPE-NEXT: crand 4*cr5+lt, 4*cr6+gt, 4*cr5+gt
-; SPE-NEXT: crand 4*cr5+lt, 4*cr7+lt, 4*cr5+lt
+; SPE-NEXT: evmergelo r6, r7, r8
+; SPE-NEXT: efdcmpeq cr0, r6, r6
+; SPE-NEXT: efdcmpeq cr1, r5, r5
+; SPE-NEXT: efdcmplt cr5, r5, r6
+; SPE-NEXT: crand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT: crandc 4*cr5+lt, 4*cr6+lt, 4*cr5+gt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
@@ -299,15 +278,13 @@ define i32 @test_f64_olt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_ole_s:
; SPE: # %bb.0:
-; SPE-NEXT: evmergelo r7, r7, r8
; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmpgt cr0, r5, r7
-; SPE-NEXT: efdcmpgt cr1, r5, r7
-; SPE-NEXT: efdcmpeq cr5, r7, r7
-; SPE-NEXT: efdcmpeq cr6, r5, r5
-; SPE-NEXT: crnor 4*cr7+lt, gt, 4*cr1+gt
-; SPE-NEXT: crand 4*cr5+lt, 4*cr6+gt, 4*cr5+gt
-; SPE-NEXT: crand 4*cr5+lt, 4*cr7+lt, 4*cr5+lt
+; SPE-NEXT: evmergelo r6, r7, r8
+; SPE-NEXT: efdcmpeq cr0, r6, r6
+; SPE-NEXT: efdcmpeq cr1, r5, r5
+; SPE-NEXT: efdcmpgt cr5, r5, r6
+; SPE-NEXT: crand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT: crandc 4*cr5+lt, 4*cr6+lt, 4*cr5+gt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
@@ -372,17 +349,13 @@ define i32 @test_f64_ueq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_ugt_s:
; SPE: # %bb.0:
+; SPE-NEXT: evmergelo r7, r7, r8
; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: evmergelo r6, r7, r8
-; SPE-NEXT: efdcmpeq cr0, r6, r6
-; SPE-NEXT: efdcmpeq cr1, r6, r6
-; SPE-NEXT: efdcmpeq cr5, r5, r5
-; SPE-NEXT: efdcmpeq cr6, r5, r5
-; SPE-NEXT: efdcmpgt cr7, r5, r6
-; SPE-NEXT: crnor 4*cr1+lt, gt, 4*cr1+gt
-; SPE-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr1+lt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr7+gt, 4*cr5+lt
+; SPE-NEXT: efdcmpeq cr0, r5, r5
+; SPE-NEXT: efdcmpeq cr1, r7, r7
+; SPE-NEXT: efdcmpgt cr5, r5, r7
+; SPE-NEXT: crnand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr6+lt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
@@ -398,11 +371,10 @@ define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-NEXT: evmergelo r7, r7, r8
; SPE-NEXT: evmergelo r5, r5, r6
; SPE-NEXT: efdcmplt cr0, r5, r7
-; SPE-NEXT: efdcmplt cr1, r5, r7
-; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
-; SPE-NEXT: # %bb.1:
-; SPE-NEXT: ori r3, r4, 0
+; SPE-NEXT: bc 12, gt, .LBB23_1
+; SPE-NEXT: blr
+; SPE-NEXT: .LBB23_1:
+; SPE-NEXT: addi r3, r4, 0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"uge", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -412,17 +384,13 @@ define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_ult_s:
; SPE: # %bb.0:
+; SPE-NEXT: evmergelo r7, r7, r8
; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: evmergelo r6, r7, r8
-; SPE-NEXT: efdcmpeq cr0, r6, r6
-; SPE-NEXT: efdcmpeq cr1, r6, r6
-; SPE-NEXT: efdcmpeq cr5, r5, r5
-; SPE-NEXT: efdcmpeq cr6, r5, r5
-; SPE-NEXT: efdcmplt cr7, r5, r6
-; SPE-NEXT: crnor 4*cr1+lt, gt, 4*cr1+gt
-; SPE-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr1+lt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr7+gt, 4*cr5+lt
+; SPE-NEXT: efdcmpeq cr0, r5, r5
+; SPE-NEXT: efdcmpeq cr1, r7, r7
+; SPE-NEXT: efdcmplt cr5, r5, r7
+; SPE-NEXT: crnand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr6+lt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
@@ -438,11 +406,10 @@ define i32 @test_f64_ule_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-NEXT: evmergelo r7, r7, r8
; SPE-NEXT: evmergelo r5, r5, r6
; SPE-NEXT: efdcmpgt cr0, r5, r7
-; SPE-NEXT: efdcmpgt cr1, r5, r7
-; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
-; SPE-NEXT: # %bb.1:
-; SPE-NEXT: ori r3, r4, 0
+; SPE-NEXT: bc 12, gt, .LBB25_1
+; SPE-NEXT: blr
+; SPE-NEXT: .LBB25_1:
+; SPE-NEXT: addi r3, r4, 0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ule", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -455,11 +422,10 @@ define i32 @test_f64_une_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-NEXT: evmergelo r7, r7, r8
; SPE-NEXT: evmergelo r5, r5, r6
; SPE-NEXT: efdcmpeq cr0, r5, r7
-; SPE-NEXT: efdcmpeq cr1, r5, r7
-; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
-; SPE-NEXT: # %bb.1:
-; SPE-NEXT: ori r3, r4, 0
+; SPE-NEXT: bc 12, gt, .LBB26_1
+; SPE-NEXT: blr
+; SPE-NEXT: .LBB26_1:
+; SPE-NEXT: addi r3, r4, 0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"une", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -469,15 +435,11 @@ define i32 @test_f64_une_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_uno_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_uno_s:
; SPE: # %bb.0:
+; SPE-NEXT: evmergelo r7, r7, r8
; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: evmergelo r6, r7, r8
-; SPE-NEXT: efdcmpeq cr0, r6, r6
-; SPE-NEXT: efdcmpeq cr1, r6, r6
-; SPE-NEXT: efdcmpeq cr5, r5, r5
-; SPE-NEXT: efdcmpeq cr6, r5, r5
-; SPE-NEXT: crnor 4*cr7+lt, gt, 4*cr1+gt
-; SPE-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr7+lt
+; SPE-NEXT: efdcmpeq cr0, r5, r5
+; SPE-NEXT: efdcmpeq cr1, r7, r7
+; SPE-NEXT: crnand 4*cr5+lt, 4*cr1+gt, gt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
index 438e1768beabf..338f2a5efca32 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
@@ -1540,11 +1540,8 @@ define i32 @fcmp_ole_f128(fp128 %a, fp128 %b) #0 {
; P9-LABEL: fcmp_ole_f128:
; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3
-; P9-NEXT: xscmpuqp cr1, v2, v3
; P9-NEXT: li r3, 1
-; P9-NEXT: crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT: crnor 4*cr5+gt, gt, 4*cr1+gt
-; P9-NEXT: crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr5+lt, un, gt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -1629,11 +1626,8 @@ define i32 @fcmp_oge_f128(fp128 %a, fp128 %b) #0 {
; P9-LABEL: fcmp_oge_f128:
; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3
-; P9-NEXT: xscmpuqp cr1, v2, v3
; P9-NEXT: li r3, 1
-; P9-NEXT: crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT: crnor 4*cr5+gt, lt, 4*cr1+lt
-; P9-NEXT: crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr5+lt, un, lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -1734,11 +1728,8 @@ define i32 @fcmp_one_f128(fp128 %a, fp128 %b) #0 {
; P9-LABEL: fcmp_one_f128:
; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3
-; P9-NEXT: xscmpuqp cr1, v2, v3
; P9-NEXT: li r3, 1
-; P9-NEXT: crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT: crnor 4*cr5+gt, eq, 4*cr1+eq
-; P9-NEXT: crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr5+lt, un, eq
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -2136,11 +2127,8 @@ define i32 @fcmps_ole_f128(fp128 %a, fp128 %b) #0 {
; P9-LABEL: fcmps_ole_f128:
; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3
-; P9-NEXT: xscmpoqp cr1, v2, v3
; P9-NEXT: li r3, 1
-; P9-NEXT: crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT: crnor 4*cr5+gt, gt, 4*cr1+gt
-; P9-NEXT: crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr5+lt, un, gt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -2225,11 +2213,8 @@ define i32 @fcmps_oge_f128(fp128 %a, fp128 %b) #0 {
; P9-LABEL: fcmps_oge_f128:
; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3
-; P9-NEXT: xscmpoqp cr1, v2, v3
; P9-NEXT: li r3, 1
-; P9-NEXT: crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT: crnor 4*cr5+gt, lt, 4*cr1+lt
-; P9-NEXT: crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr5+lt, un, lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -2330,11 +2315,8 @@ define i32 @fcmps_one_f128(fp128 %a, fp128 %b) #0 {
; P9-LABEL: fcmps_one_f128:
; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3
-; P9-NEXT: xscmpoqp cr1, v2, v3
; P9-NEXT: li r3, 1
-; P9-NEXT: crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT: crnor 4*cr5+gt, eq, 4*cr1+eq
-; P9-NEXT: crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr5+lt, un, eq
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
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