[PATCH] D135024: [PowerPC] Fix invalid cast for vector shuffles when lowering to the xxsplti32dx instruction.

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/p10-splatImm32-undef.ll:35-60
+; CHECK-AIX-NEXT:    stxv vs52, 112(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs53, 128(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs54, 144(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs55, 160(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs56, 176(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs57, 192(r1) # 16-byte Folded Spill
+; CHECK-AIX-NEXT:    stxv vs58, 208(r1) # 16-byte Folded Spill
----------------
ZarkoCA wrote:
> These register spills are not seen with any other target in the test case. Is this maybe an artifact of the test case, or something else? What happens on Linux 64 BE? 
Seems unrelated to this patch but nonetheless it is bad. @amyk can you please pre-commit the test case?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135024/new/

https://reviews.llvm.org/D135024