[PATCH] D135869: [AMDGPU][DAG] Only apply trunc/shift combine to 16 bit types

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

What are you trying to solve here? alignbit isn't preferable to 32-bit shifts, and the shift doesn't seem to be wrong <https://alive2.llvm.org/ce/z/PKEdNk>



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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3240
   //     i16 (trunc (srl (i32 (trunc x), K)))
-  if (VT.getScalarSizeInBits() < 32) {
+  if (VT.getScalarSizeInBits() == 16) {
     EVT SrcVT = Src.getValueType();
----------------
Legal 16-bit isn't the point here, it's to avoid the 64-bit shift. Even if we didn't have 16-bit types we would want the combine. 


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Comment at: llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll:157
+;
+; Thus, we should have an alignbit here and not a lshrrev
+define i32 @trunc_srl_i64_25_to_i26(i64 %x) {
----------------
The alignbit and shift are equally fast, and the shift is easier to understand


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  https://reviews.llvm.org/D135869/new/

https://reviews.llvm.org/D135869