[PATCH] D135455: [AArch64] SME2 Single-multi vector ternary int/FP 2 and 4 registers

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:1043
 
+def ZZ_s_r  : RegisterOperand<ZPR2, "printTypedVectorList<0,'s',/*Stride=*/2,/*PrintRange=*/true>"> {
+  let ParserMatchClass = ZPRVectorList<32, 2>;
----------------
For a vector-list of consecutive registers we should align NEON, SVE and SME2 here, such that:

  {z0.s, z1.s} vs {z0.s - z1.s} -> prefer {z0.s, z1.s}
  {z0.s, z1.s, z2.s} vs {z0.s - z2.s} -> prefer {z0.s - z2.s}
  {z0.s, z1.s, z2.s, z3.s} vs {z0.s - z3.s} -> prefer {z0.s - z3.s}

This means that we don't need a special `ZZ_s_r`, and we should change ZZZ_* and ZZZZ_* to print the range form (rather than adding new ZZZZ_*_r`  forms as you did in this patch).

Changing this for SVE(2) also means updating the corresponding tests. Can you pull those changes out into a separate patch and then rebase this patch on top?


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Comment at: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp:1429
 
+template <unsigned Stride>
 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
----------------
s/Stride/N/


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Comment at: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp:1493
 
-template <unsigned NumLanes, char LaneKind>
+template <unsigned Stride>
+void AArch64InstPrinter::printVectorRange(const MCInst *MI, unsigned OpNum,
----------------
Stride is a misnomer, because the stride is actually '1' (the registers are consecutive). This should be 'N', the number of registers in the range.


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Comment at: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp:1506
+
+template <unsigned NumLanes, char LaneKind, unsigned Stride, bool PrintRange>
 void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
----------------
This should be `N`, not stride.


Repository:
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  https://reviews.llvm.org/D135455/new/

https://reviews.llvm.org/D135455